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smsc lpc47m172 smsc/non-smsc register sets ( rev. 01-11-07) datasheet lpc47m172 advanced i/o controller with motherboard glue logic datasheet product features ? 3.3v operation (5v tolerant) ? lpc interface ? multiplexed command, address and data bus ? serial irq interface compatible with serialized irq support for pci systems ? acpi 1.0b/2.0 compliant ? programmable wake-up event interface ? pc99a/pc2001 compliant ? general purpose input/output pins (13) ? fan tachometer inputs (2) ? green and yellow power leds ? isa plug-and-play compatible register set ? motherboard glue logic ? 5v reference generation ? 5v standby reference generation ? ide reset/buffered pci reset outputs ? power ok signal generation ? power sequencing ? power supply turn on circuitry ? resume reset signal generation ? hard drive front panel led ? voltage translation for ddc to vga monitor ? smbus isolation circuitry ? cnr dynamic down control ? 2.88mb super i/o floppy disk controller ? licensed cmos 765b floppy disk controller ? software and register compatible with smsc's proprietary 82077aa compatible core ? supports one floppy drive ? configurable open drain/push-pull output drivers ? supports vertical recording format ? 16-byte data fifo ? 100% ibm compatibility ? detects all overrun and underrun conditions ? sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption ? dma enable logic ? data rate and drive control registers ? 480 address, up to eight irq and three dma options ? enhanced digital data separator ? 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates ? programmable precompensation modes ? keyboard controller ? 8042 software compatible ? 8 bit microcomputer ? 2k bytes of program rom ? 256 bytes of data ram ? four open drain outputs dedicated for keyboard/mouse interface ? asynchronous access to two data registers and one status register ? supports interrupt and polling access ? 8 bit counter timer ? port 92 support ? fast gate a20 and kreset outputs ? serial ports ? two full function serial ports ? high speed 16c550a compatible uart with send/receive 16-byte fifos ? supports 230k and 460k baud ? programmable baud rate generator ? modem control circuitry ? 480 address and 15 irq options ? infrared port ? multiprotocol infrared interface ? 32-byte data fifo ? irda 1.0 compliant ? sharp ask ir ? hp-sir ? 480 address, up to 15 irq and three dma options ? multi-mode parallel port with chiprotect ? standard mode ibm pc/xt , pc/at, and ps/2 compatible bi-directional parallel port ? enhanced parallel port (epp) compatible - epp 1.7 and epp 1.9 (ieee 1284 compliant) ? ieee 1284 compliant enhanced capabilities port (ecp) ? chiprotect circuitry for protection ? 960 address, up to 15 irq and three dma options ? interrupt generating registers ? registers generate irq1 ? irq15 on serial irq interface. ? xor-chain board test ? 128 pin mqfp lead-free rohs compliant package, 3.2 mm footprint
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 2 smsc lpc47m172 datasheet ordering information order number: LPC47M172-NW for 128 pin, mqfp lead-free rohs compliant package (3.2mm footprint) 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? 2007 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for c onstruction purposes is not necessarily given. although the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent ri ghts or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (t he "terms of sale agreement"). the product may contain design def ects or errors known as anomalies which may caus e the product's functions to deviate from publis hed specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where produc t failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at t he risk of the customer. copies of this do cument or other smsc literature, as wel l as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www .smsc.com. smsc is a registered trademark of standard micros ystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitn ess for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usag e of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or othe rwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 3 smsc lpc47m172 datasheet table of contents chapter 1 general de scription............................................................................................................ .. 11 chapter 2 pin lay out ..................................................................................................................... ....... 12 chapter 3 description of pi n functions ................................................................................................ 14 3.1 buffer name descrip tions ....................................................................................................... ...................22 3.2 pins with inter nal resi stors ................................................................................................... ....................23 3.3 pins that require ex ternal re sistors........................................................................................... ..............23 3.4 default stat e of pins.......................................................................................................... .........................24 chapter 4 block diagram .................................................................................................................. .... 28 chapter 5 power and clock fu nctionality ............................................................................................. 29 5.1 3 volt operation / 5 volt to lerance ............................................................................................ ................29 5.2 vcc po wer ...................................................................................................................... ..........................29 5.3 vtr power...................................................................................................................... ...........................29 5.3.1 trickle power f unctiona lity .................................................................................................... .............30 5.4 v5p0_stby power ................................................................................................................ ....................30 5.5 32.768 khz trickl e clock in put................................................................................................. ..................30 5.5.1 indication of 32khz clock ...................................................................................................... .............30 5.6 14.318 mhz cl ock i nput ......................................................................................................... ....................31 5.7 internal pwrgood ............................................................................................................... ....................31 5.8 maximum curr ent va lues......................................................................................................... ..................31 5.9 power management ev ents (pme /sci) .............................................................................................. .......31 chapter 6 functional de scription......................................................................................................... .32 6.1 super i/o r egisters............................................................................................................ ........................32 6.2 host processor in terface (lpc) ................................................................................................. ................33 6.3 lpc inte rface .................................................................................................................. ...........................33 6.3.1 lpc interface sign al definition ................................................................................................ ...........33 6.3.2 lpc c ycles ..................................................................................................................... ....................33 6.3.3 field defi nitions.............................................................................................................. .....................33 6.3.4 nlframe usage.................................................................................................................. ..............34 6.3.5 i/o read and writ e cycl es...................................................................................................... ............34 6.3.6 dma read and write c ycles ...................................................................................................... ........34 6.3.7 dma prot ocol ................................................................................................................... ...................34 6.3.8 power mana gement ............................................................................................................... .............35 6.3.9 sync prot ocol .................................................................................................................. ..................35 6.3.10 i/o and dma star t fiel ds....................................................................................................... ......36 6.3.11 lpc trans fers .................................................................................................................. ...............36 6.4 floppy disk co ntroll er ......................................................................................................... .......................37 6.4.1 fdc configurati on regist ers .................................................................................................... ..........37 6.4.2 fdc internal regist ers......................................................................................................... ...............37 6.4.3 status regist er a (sra) ........................................................................................................ .............38 6.4.4 status regist er b (srb) ........................................................................................................ .............39 6.4.5 digital output r egister (dor).................................................................................................. ...........41 6.4.6 tape drive regi ster (tdr) ...................................................................................................... ...........42 6.4.7 data rate select register (dsr)................................................................................................ ........43 6.4.8 main status regi ster........................................................................................................... ................45 6.4.9 data regist er (fifo)........................................................................................................... ................46 6.4.10 digital input r egister (dir)................................................................................................... ...........47 6.4.11 configuration control regi ster (ccr) ........................................................................................... ..48 6.4.12 status regist er enc oding ....................................................................................................... .........49 6.5 modes of o peratio n............................................................................................................. .......................51 6.5.1 pc/at mode ..................................................................................................................... ..................51 6.5.2 ps/2 m ode ...................................................................................................................... ....................51 6.5.3 model 30 mode .................................................................................................................. .................51 6.6 dma trans fers .................................................................................................................. .........................51 6.7 controller phases.............................................................................................................. .........................52 6.7.1 command phase .................................................................................................................. ..............52 6.7.2 execution phase ................................................................................................................ .................52 6.8 data transfer terminat ion ...................................................................................................... ...................53
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 4 smsc lpc47m172 datasheet 6.9 result phase................................................................................................................... ...........................53 6.10 command set/d escrip tions ....................................................................................................... .............53 6.10.1 instructi on se t................................................................................................................ ..................56 6.11 data transfe r comma nds ......................................................................................................... .............62 6.11.1 read data ...................................................................................................................... .................62 6.12 read dele ted da ta .............................................................................................................. ...................63 6.13 read a track................................................................................................................... .......................64 6.14 write data..................................................................................................................... ..........................65 6.15 write dele ted da ta ............................................................................................................. ....................65 6.16 verify ......................................................................................................................... .............................65 6.17 format a track ................................................................................................................. ......................66 6.18 control comm ands ............................................................................................................... ..................68 6.18.1 read id ........................................................................................................................ ...................68 6.18.2 recalibr ate .................................................................................................................... ..................68 6.18.3 seek ........................................................................................................................... .....................68 6.19 sense interr upt status ......................................................................................................... ...................69 6.20 sense driv e stat us ............................................................................................................. ....................70 6.21 specif y........................................................................................................................ ............................70 6.22 confi gure ...................................................................................................................... ..........................70 6.22.1 configure defa ult va lues....................................................................................................... ..........70 6.23 version ........................................................................................................................ ...........................71 6.24 relative seek .................................................................................................................. .......................71 6.25 perpendicu lar m ode............................................................................................................. ...................72 6.26 lock ........................................................................................................................... .............................73 6.27 enhanced dumpreg ............................................................................................................... .............74 6.27.1 compatib ility .................................................................................................................. ..................74 6.28 serial port (uart)............................................................................................................. .....................74 6.28.1 register de scription ........................................................................................................... .............74 6.28.2 receive buffer r egister (rb) ................................................................................................... .......75 6.28.3 transmit buffer r egister (tb).................................................................................................. ........75 6.28.4 interrupt enable register (ier) ................................................................................................ .......75 6.28.5 fifo control r egister (fcr).................................................................................................... .......76 6.28.6 interrupt identificatio n register (iir)........................................................................................ ........76 6.28.7 line control r egister (lcr) .................................................................................................... ........78 6.28.8 modem control r egister (mcr) ................................................................................................... ...79 6.28.9 line status re gister (lsr) ..................................................................................................... .........80 6.28.10 modem status r egister (msr).................................................................................................... ....81 6.28.11 scratchpad regi ster (scr) ...................................................................................................... .......82 6.29 programmable baud rate generator (a nd divisor latches dlh, dll) .................................................82 6.29.1 effect of the rese t on regist er file ........................................................................................... ....83 6.29.2 fifo interrupt mode oper ation .................................................................................................. .....83 6.29.3 fifo polled m ode operat ion..................................................................................................... ......84 chapter 7 notes on serial po rt operat ion ........................................................................................... 88 7.1 fifo mode o peratio n: ........................................................................................................... ....................88 7.1.1 general ........................................................................................................................ .......................88 7.1.2 tx and rx fifo operat ion....................................................................................................... ..........88 7.2 infrared in terface ............................................................................................................. ...........................89 7.3 parallel port.................................................................................................................. ..............................89 7.4 ibm xt/at compatible, bi-d irectional an d epp modes ............................................................................. 91 7.4.1 data port ...................................................................................................................... .......................91 7.4.2 status port .................................................................................................................... ......................91 7.4.3 control port ................................................................................................................... ......................92 7.4.4 epp addre ss po rt ............................................................................................................... ................93 7.4.5 epp data po rt 0................................................................................................................ ..................93 7.4.6 epp data po rt 1................................................................................................................ ..................93 7.4.7 epp data po rt 2................................................................................................................ ..................93 7.4.8 epp data po rt 3................................................................................................................ ..................94 7.5 epp 1.9 oper ation .............................................................................................................. .......................94 7.5.1 software cons traints........................................................................................................... ................94 7.6 epp 1.9 wr ite.................................................................................................................. ...........................94
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 5 smsc lpc47m172 datasheet 7.7 epp 1.9 read ................................................................................................................... .........................95 7.8 epp 1.7 oper ation .............................................................................................................. .......................95 7.8.1 software cons traints........................................................................................................... ................95 7.9 epp 1.7 wr ite.................................................................................................................. ...........................96 7.10 epp 1.7 read ................................................................................................................... ......................96 7.10.1 extended capabilities parallel port ............................................................................................ .....97 7.10.2 vocabu lary..................................................................................................................... ..................97 7.11 ecp implementat ion stan dard .................................................................................................... ...........98 7.11.1 descrip tion.................................................................................................................... ...................98 7.12 register de finiti ons........................................................................................................... ......................99 7.12.1 data and ecpa fifo port ......................................................................................................... ........100 7.12.2 device status r egister (dsr)................................................................................................... .......101 7.12.3 device control r egister (dcr) .................................................................................................. ......101 7.12.4 cfifo (parallel po rt data fifo) ................................................................................................ ...102 7.12.5 ecpdfifo (ecp data fifo) ....................................................................................................... .102 7.12.6 tfifo (test fifo mode) ......................................................................................................... .........102 7.12.7 cnfga (configurati on regist er a) ............................................................................................... ....103 7.12.8 cnfgb (configurati on regist er b) ............................................................................................... ....103 7.12.9 ecr (extended cont rol regi ster) ................................................................................................ ....103 7.13 operat ion...................................................................................................................... ........................106 7.13.1 mode switching/so ftware c ontrol................................................................................................ ..106 7.14 ecp oper ation .................................................................................................................. ...................106 7.15 termination from ecp mode ...................................................................................................... ..........107 7.16 command/d ata................................................................................................................... ..................107 7.17 data comp ression ............................................................................................................... .................107 7.18 pin defi nition ................................................................................................................. .......................107 7.19 lpc connec tions................................................................................................................ ..................108 7.20 interr upts ..................................................................................................................... .........................108 7.21 fifo operation................................................................................................................. ....................108 7.21.1 dma trans fers .................................................................................................................. ............109 7.21.2 dma mode - transfers from the fifo to the ho st.........................................................................109 7.21.3 programmed i/o mode or non-dma mode ...................................................................................109 7.21.4 programmed i/o - transfers from the fifo to the ho st ................................................................109 7.21.5 programmed i/o - transfers from the host to the fi fo ................................................................110 7.22 power ma nagem ent............................................................................................................... ...............110 7.23 serial irq ..................................................................................................................... ........................110 7.23.1 timing diagrams for ser_irq c ycle ..........................................................................................110 7.23.2 ser_irq cycl e cont rol .......................................................................................................... ......111 7.23.3 ser_irq data frame............................................................................................................. ......112 7.23.4 stop cycle control............................................................................................................. ............112 7.23.5 latenc y ........................................................................................................................ ..................113 7.23.6 eoi/isr read latenc y ........................................................................................................... .......113 7.23.7 ac/dc specific ation i ssue ...................................................................................................... ......113 7.23.8 reset and init ializa tion ....................................................................................................... ...........113 7.24 interrupt generat ing regi sters ................................................................................................. ............113 7.25 8042 keyboard controll er descri ption ........................................................................................... .......114 7.25.1 keyboard in terface ............................................................................................................. ...........114 7.25.2 keyboard da ta write ............................................................................................................ .........115 7.25.3 keyboard da ta r ead ............................................................................................................. ........115 7.25.4 keyboard comm and wr ite ......................................................................................................... ...115 7.25.5 keyboard st atus read ........................................................................................................... .......115 7.25.6 cpu-to-host co mmunica tion ...................................................................................................... ..115 7.25.7 host-to-cpu co mmunica tion ...................................................................................................... ..115 7.25.8 kirq........................................................................................................................... ...................115 7.25.9 mirq ........................................................................................................................... ..................116 7.25.10 external keyboard an d mouse inte rface .......................................................................................116 7.25.11 keyboard powe r management ...................................................................................................... 116 7.25.12 soft power do wn m ode........................................................................................................... ......116 7.25.13 hard power down mode ........................................................................................................... ....116 7.25.14 interr upts ..................................................................................................................... ..................117
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 6 smsc lpc47m172 datasheet 7.25.15 memory conf igurat ions .......................................................................................................... .......117 7.25.16 register de finiti ons ........................................................................................................... ............117 7.25.17 external cl ock si gnal .......................................................................................................... ..........118 7.25.18 default reset condit ions ....................................................................................................... ........118 7.25.19 gatea20 and keyb oard re set..................................................................................................... ..118 7.26 port 92 fast gatea20 and keyboar d rese t........................................................................................ ..118 7.26.1 port 92 re gister............................................................................................................... ..............118 7.26.2 keyboard and mouse pme generat ion .........................................................................................122 7.27 general pu rpose i/o............................................................................................................ .................123 7.27.1 gpio pi ns ...................................................................................................................... ...............124 7.27.2 descrip tion.................................................................................................................... .................124 7.27.3 gpio cont rol ................................................................................................................... ..............125 7.27.4 gpio oper ation................................................................................................................. ............126 7.27.5 gpio pme func tiona lity......................................................................................................... .......127 7.27.6 either edge tri ggered inte rrupts ............................................................................................... ....127 7.28 pme s upport .................................................................................................................... ....................127 7.28.1 ?wake on spec ific key? option.................................................................................................. .....128 7.29 fan moni toring................................................................................................................. .....................129 7.29.1 fan tachomet er i nputs .......................................................................................................... .......130 7.29.2 detection of a stalled fan ..................................................................................................... ........130 7.30 hard drive and power le d logic ................................................................................................. ........131 7.30.1 hard drive front panel le d (r ed) ............................................................................................... .131 7.30.2 yellow and green po wer led pins ...............................................................................................1 32 7.31 power genera tion (5 v) .......................................................................................................... ...............133 7.31.1 referenc e pins ................................................................................................................. .............133 7.31.2 5v main refer ence gene ration ................................................................................................... ..134 7.31.3 5v standby refer ence gene ration................................................................................................ 134 7.31.4 reference timings .............................................................................................................. ..........135 7.32 ide reset ou tput pin ........................................................................................................... ................135 7.33 pci reset ou tput pins .......................................................................................................... ................135 7.34 voltage transla tion circ uit.................................................................................................... ................136 7.35 smbus isolatio n circu itry...................................................................................................... ................138 7.36 ps_on logic .................................................................................................................... ....................140 7.37 pwrgd_3v logic ................................................................................................................. ...............140 7.38 sck_bjt_gate out put ............................................................................................................ ..........142 7.39 backfeed cut and latched ba ckfeed cut circ uitry ...............................................................................1 43 7.40 resume re set logi c ............................................................................................................. ...............148 7.41 cnr logi c ...................................................................................................................... ......................148 chapter 8 power control runt ime registers...................................................................................... 150 chapter 9 gpio runtime registers.................................................................................................... 157 chapter 10 runtime register block runtime regi sters ....................................................................... 161 chapter 11 configur ation .................................................................................................................. .... 172 11.1 system elements................................................................................................................ ..................172 11.1.1 primary configuration address de coder .......................................................................................172 11.1.2 entering the conf iguration state............................................................................................... .....172 11.1.3 exiting the confi guration state ................................................................................................ ......172 11.1.4 configurati on sequ ence ......................................................................................................... .......173 11.1.5 enter configur ation mode....................................................................................................... .......173 11.1.6 configurat ion m ode ............................................................................................................. ..........173 11.1.7 exit configur ation mode ........................................................................................................ ........173 11.1.8 programming example ............................................................................................................ ......174 11.2 chip level (global) c ontrol/config uration register s[0x00-0x2f] .........................................................179 11.3 logical device confi guration/control regist ers [0x30- 0xff] ...............................................................182 11.4 logical device i/o addr ess ..................................................................................................... .............186 11.5 logical device confi guration r egister s ......................................................................................... .......189 chapter 12 electrical characteristics .................................................................................................... 1 95 12.1 maximum guarant eed rati ngs ..................................................................................................... ........195 12.2 operational dc c haracteristics ................................................................................................. ...........195 12.3 standby power r equirem ents ..................................................................................................... .........200 12.4 capacitance valu es for pins.................................................................................................... .............201
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 7 smsc lpc47m172 datasheet chapter 13 timing di agrams ................................................................................................................ 202 13.1 ecp parallel port ti ming ....................................................................................................... ...............211 13.1.1 parallel port fifo (m ode 101) .................................................................................................. .....211 13.1.2 ecp parallel port timing ....................................................................................................... ........211 13.1.3 forward- idle ................................................................................................................... ...............211 13.1.4 forward data tr ansfer p hase .................................................................................................... ...211 13.1.5 reverse-idle phase ............................................................................................................. ..........211 13.1.6 reverse data tr ansfer p hase .................................................................................................... ...211 13.1.7 output dr ivers ................................................................................................................. ..............212 chapter 14 package ou tline ................................................................................................................ . 223 chapter 15 board test mode................................................................................................................ 224 chapter 16 reference do cuments........................................................................................................ 226 list of figures figure 2.1 - lpc 47m172 pin layout .............................................................................................. ..............................12 figure 4.1 - lpc47m 172 block diagr am........................................................................................... ...........................28 figure 7.1 - nk bdrst cir cuit................................................................................................... .................................120 figure 7.2 - ke yboard latch.................................................................................................... ...................................121 figure 7.3 - mouse latch ....................................................................................................... ....................................121 figure 7.4 - gpio func tion illust ration........................................................................................ ...............................126 figure 7.5 - fan tachometer input and cl ock s ource ............................................................................. ..................130 figure 7.6 - n hd_led cir cuit ................................................................................................... .................................132 figure 7.7 - ylw_le d/grn_led circuit ........................................................................................... .......................133 figure 7.8 - re f5v cir cuit ..................................................................................................... ....................................134 figure 7.9 - ref5v_ stby........................................................................................................ .................................135 figure 7.10 - vga ddc volt age translati on circu it.............................................................................. .....................138 figure 7.11 - smbus isolation circu it.......................................................................................... ..............................139 figure 7.12 - pwrgd_3v circu it, discrete im plementa tion ........................................................................ ..............141 figure 7.13 - pwrgd_3v circuit in lpc47m 172 .................................................................................... ..................141 figure 7.14 - nf prst timing.................................................................................................... ................................142 figure 7.15 - sck_ bjt_gate circu it ............................................................................................. ............................143 figure 7.16 - backfeed cut and latched backf eed cut cir cuit .................................................................... ..............144 figure 7.17 - latched backfe ed cut power up sequence........................................................................... ..............145 figure 7.18 - latched ba ckfeed cut se quence 1 .................................................................................. ....................145 figure 7.19 - latched ba ckfeed cut se quence 2 .................................................................................. ....................146 figure 7.20 - latched ba ckfeed cut fl owchart ................................................................................... .......................147 figure 7.21 - cnr cir cuit ...................................................................................................... .....................................149 figure 13.1 - po wer-up ti ming .................................................................................................. ................................203 figure 13.2 - i nput clock timing ............................................................................................... .................................204 figure 13.3 - pc i clock ti ming ................................................................................................. .................................204 figure 13.4 - reset ti ming ..................................................................................................... ....................................204 figure 13.5 - output timing measur ement conditions , lpc si gnals ................................................................ .........205 figure 13.6 - input timing measur ement conditions, lpc sign als................................................................. ...........205 figure 13.7 - i/o write........................................................................................................ ........................................205 figure 13.8 - i/o read ......................................................................................................... ......................................206 figure 13.9 - dma request assertion th rough nldrq .............................................................................. ...............206 figure 13.10 - dma wr ite (first byte) .......................................................................................... ..............................206 figure 13.11 - dma re ad (first byte)........................................................................................... .............................206 figure 13.12 - floppy disk dr ive timing (at mode on ly) ......................................................................... ..................207 figure 13.13 - epp 1.9 data or address wr ite cycle............................................................................. ....................208 figure 13.14 - epp 1.9 data or address read cycle .............................................................................. ..................209 figure 13.15 - epp 1.7 data or address wr ite cycle............................................................................. ....................210 figure 13.16 - epp 1.7 data or address read cycle .............................................................................. ..................210 figure 13.17 - parallel port fifo timing ....................................................................................... ............................212 figure 13.18 - ecp parallel port forward timing ................................................................................ ......................213 figure 13.19 - ecp parallel port reve rse ti ming ................................................................................ ......................214 figure 13.20 - set up and hold time ............................................................................................. .............................215 figure 13.21 - seri al port data................................................................................................ ...................................215
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 8 smsc lpc47m172 datasheet figure 13.22 - keyboard/mouse receive/send da ta ti ming ......................................................................... ............216 figure 13.23 - fan tac hometer input timing ..................................................................................... ........................217 figure 13.24 - power led output timing ......................................................................................... ..........................217 figure 13.25 - ref5v/ref5v_stby output when vcc/ vtr ramps up before vcc5v/ v_5p 0_stby ...............218 figure 13.26 - ref5v/ref5v_stby output when vcc5 v/ v_5p0_stby ramps up before v cc/vtr ...............218 figure 13.27 - ref5v/ref5v_stby output when vcc/ vtr ramps down before vcc5v/ v_5p0_stby...........219 figure 13.28 - ref5v/ref5v_stby output when vcc5 v/ v_5p0_stby ramps down before vcc/vtr...........219 figure 13.29 - rise, fall and propagati on timi ngs .............................................................................. ......................220 figure 13.30 - reseme reset s equence ........................................................................................... ........................222 figure 14.1 - 128 pin mqfp package outlin e, 14x20x2.7 body, 3.2mm foot print.................................................... 223 figure 15.1 - example xor chain circuitry...................................................................................... .........................224 list of tables table 3.1 - lpc47m 172 pin descr iption .......................................................................................... ............................14 table 3.2 - pins with internal re sistors....................................................................................... .................................23 table 3.3 - pins that requi re external resistors............................................................................... ...........................23 table 3.4 - defaul t state of pins .............................................................................................. ....................................25 table 6.1 - super i/o block logical device number and addres ses ................................................................ ...........32 table 6.2 - status, data and control registers................................................................................. ...........................37 table 6.3 - internal 2 drive decode - norm al................................................................................... ............................41 table 6.4 - internal 2 drive decode - drives 0 and 1 sw apped ................................................................... ................42 table 6.5 - tape select bits ................................................................................................... ......................................42 table 6.6 - dr ive type id ...................................................................................................... .......................................43 table 6.7 - precom pensation delays ............................................................................................. ..............................44 table 6.8 - da ta ra tes ......................................................................................................... ........................................44 table 6.9 - drv den mapp ing ..................................................................................................... ................................45 table 6.10 - default pr ecompensati on dela ys .................................................................................... .........................45 table 6.11 - fifo service delay................................................................................................ ..................................46 table 6.12 - status register 0 ................................................................................................. ....................................49 table 6.13 - status register 1 ................................................................................................. ....................................49 table 6.14 - status register 2 ................................................................................................. ....................................50 table 6.15 - status register 3 ................................................................................................. ....................................50 table 6.16 - description of command symbols .................................................................................... .......................54 table 6.17 - inst ruction set ................................................................................................... .......................................56 table 6.18 - se ctor si zes...................................................................................................... .......................................62 table 6.19 - effects of mt and n bits .......................................................................................... ................................63 table 6.20 - skip bit vs read data command..................................................................................... ........................63 table 6.21 - skip bit vs. read deleted da ta command ............................................................................ ..................64 table 6.22 - result phase table................................................................................................ ..................................64 table 6.23 - verify command result p hase t able ................................................................................. .....................66 table 6.24 - typical va lues for formatti ng ..................................................................................... .............................67 table 6.25 - interrupt identific ation.......................................................................................... .....................................69 table 6.26 - drive co ntrol delays (ms) ......................................................................................... ...............................70 table 6.27 - effects of wgate and gap bits ..................................................................................... ........................73 table 6.28 - addressi ng the seri al port ........................................................................................ ...............................74 table 6.29 - interrupt control table ........................................................................................... ..................................77 table 6.30 - baud ra tes ........................................................................................................ ......................................84 table 6.31 - reset function table .............................................................................................. .................................85 table 32 - register summary fo r an individual uart c hannel ..................................................................... ..............86 table 7.1 - paralle l port co nnector ............................................................................................ ..................................91 table 7.2 - epp pi n descrip tions ............................................................................................... ..................................96 table 7.3 - ecp pin descr iptions............................................................................................... ..................................99 table 7.4 - ecp regi ster defi nitions........................................................................................... ...............................100 table 7.5 - m ode descrip tions .................................................................................................. .................................100 table 7.6 - extended control r egist er .......................................................................................... .............................105 table 7.7 - programming for confi guration register b (bit s 5:3) ................................................................ ...............105 table 7.8 - programming for confi guration register b (bit s 2:0) ................................................................ ...............105 table 7.9 - channel/data comm ands supported in ecp mode ........................................................................ .........107
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 9 smsc lpc47m172 datasheet table 7.10 - i/o address map ................................................................................................... .................................114 table 7.11 - host interfac e fl ags .............................................................................................. .................................115 table 7.12 - stat us regi ster ................................................................................................... ...................................117 table 7.13 - keyboard and mouse pi n/register re set va lues ...................................................................... ............118 table 7.14 - keyboard port 92 regist er......................................................................................... ............................119 table 7.15 - na20m truth table ................................................................................................. ...............................120 table 7.16 - gpio summary...................................................................................................... ................................124 table 7.17 - general purpos e i/o port assignm ents .............................................................................. ...................125 table 7.18 - gpio conf iguration summary ........................................................................................ .......................125 table 7.19 - gpio r ead/write b ehavio r .......................................................................................... ..........................126 table 7.20 - hard driv e front p anel pi ns ....................................................................................... ...........................131 table 7.21 - nhd_le d truth table............................................................................................... .............................131 table 7.22 - led pi ns .......................................................................................................... ......................................132 table 7.23 - led truth t able................................................................................................... ..................................132 table 7.24 - referenc e generati on pi ns......................................................................................... ...........................133 table 7.25 - ref5v ............................................................................................................. ......................................134 table 7.26 - ref5v_ stby ........................................................................................................ ................................134 table 7.27 - nide _rstdrv pin ................................................................................................... .............................135 table 7.28 - nide_rst drv truth table ........................................................................................... ........................135 table 7.29 - npci rst_out pins .................................................................................................. ............................136 table 7.30 - npcirst_out and np cirst_out2 tr uth t able .......................................................................... ......136 table 7.31 - voltage translation ddc pi ns ...................................................................................... .........................136 table 7.32 - vga ddcsda vo ltage transla tion lo gic .............................................................................. ................137 table 7.33 - vga ddcscl vo ltage transla tion l ogic .............................................................................. ................137 table 7.34 - smbus isolati on pins .............................................................................................. ...............................138 table 7.35 - smb_clk isolation logic ........................................................................................... ...........................139 table 7.36 - smb_dat isolation logic ........................................................................................... ...........................139 table 7.37 - nps_on, ncpu _present and ns lp_s3 pins ............................................................................. ......140 table 7.38 - nps_on truth table................................................................................................ ..............................140 table 7.39 - pwrgd_3v, nf prst and pwrg d_ps pi ns ................................................................................ .......140 table 7.40 - pwrgd _3v truth table.............................................................................................. ..........................141 table 7.41 - sck_ bjt_gate pin .................................................................................................. ...........................142 table 7.42 - sck_bjt_ gate trut h tabl e .......................................................................................... ......................142 table 7.43 - nbackfeed_cut and latched_bf _cut pins ............................................................................. ...143 table 7.44 - nbackfeed _cut trut h tabl e ......................................................................................... ....................143 table 7.45 - latched_bf _cut trut h table ........................................................................................ ...................144 table 7.46 - latched backfeed cu t power up s equence ti ming ..................................................................... .........145 table 7.47 - latched backfeed cut sequence 1 and 2 ti ming ...................................................................... ............146 table 7.48 - nr smrst pin....................................................................................................... .................................148 table 7.49 - cnr pi ns .......................................................................................................... .....................................148 table 7.50 - cnr logi c truth table ............................................................................................. .............................149 table 8.1 - power contro l runtime regist ers summary, ld_ num bit = 0............................................................ ....150 table 8.2 - power control runtime register s description, ld _num bit = 0 ........................................................ .....151 table 9.1 - gpio runtime regi sters summary, ld_num = 0......................................................................... ..........157 table 9.2 - gpio runtime regist ers description, ld_num = 0 ..................................................................... ...........158 table 10.1 - runtime register bl ock runtime regi sters summary .................................................................. .........161 table 10.2 - runtime register blo ck runtime regist ers descr iption .............................................................. ..........162 table 11.1 - lpc47m172 configuration re gisters summary, ld _num bit = 0 ......................................................... 175 table 11.2 - lpc47m172 configurati on register summa ry, ld_num=1................................................................ ..177 table 11.3 - chip level regi sters .............................................................................................. ................................179 table 11.4 - logical device r egisters.......................................................................................... ..............................182 table 11.5 - primary interr upt select configurati on register descrip tion ....................................................... ...........184 table 11.6 - dma channel select co nfiguration regist er descr iption ............................................................. .........184 table 11.7 - logical device i/o address, ld_ num bit = 0 ........................................................................ ................186 table 11.8 - logical device i/o address, ld_num bit = 1 ....................................................................... ................187 table 11.9 - floppy disk controller logica l device configur ation regi sters ..................................................... ........189 table 11.10 - serial port 2 logical device configurat ion regi sters............................................................. ..............190 table 11.11 - parallel port logical device configurat ion regi sters ............................................................. ..............191 table 11.12 - serial port 1 logical device configurat ion regi sters............................................................. ..............192 table 11.13 - keyboard logical de vice configurat ion registers .................................................................. .............193
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 10 smsc lpc47m172 datasheet table 11.14 - power control/runtim e register block logical device configuration register s .................................193 table 12.1 - operationa l dc characte ristics.................................................................................... ..........................195 table 12.2 - s3-s5 standby curr ent ............................................................................................. .............................200 table 13.1 - nide _rstdrv timing................................................................................................ ...........................220 table 13.2 - npcirst_out and npcirst_ou t2 ti ming ............................................................................... .........220 table 13.3 - ps_ on ti ming ...................................................................................................... .................................220 table 13.4 - sck_bj t_gate timing............................................................................................... .........................221 table 13.5 - pwrg d_3v ti ming ................................................................................................... ............................221 table 13.6 - cnr codec down enabl e timi ng ...................................................................................... .................221 table 13.7 - resume reset timing............................................................................................... .............................222 table 14.1 - 128 pin mqfp package pa rameters ................................................................................... ..................223 table 15.1 - xor test pattern example.......................................................................................... ..........................225
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 11 smsc lpc47m172 datasheet chapter 1 general description the lpc47m172 is a 3.3v (5v tolerant) pc 99a/pc2001 co mpliant advanced i/o c ontroller for desktop pcs. the device, which im plements the low pin count (lpc) interface, inclu des i/o functionality as well as motherboard glue logic into a 128-pin package. this is space saving solution on the motherboard resulting in lower cost. the lpc47m172 also provides 13 general purpose pins, which offer flexibility to the system designer, and two fan tachometer inputs . the lpc47m172?s lpc interface supports lpc i/o and dma cycles. the lpc47m172 includes complete legac y i/o: a keyboard interface with ami tm bios; smsc's true cmos 765b floppy disk controller with advanced digital data separator; two 16c550a compatible uarts; one multi-mode parallel port including chiprotect ci rcuitry plus epp and ecp. the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc/a t architectures; in addition, it provides data overflow and underflow protection. the smsc?s paten ted advanced digital data separator allows for ease of testing and use. the parallel po rt is compatible with ibm pc/at architecture, as well as ieee 1284 epp and ecp. the lpc47m172 incorporates sophisticate d power control circuitry (pcc) which includes support for keyboard and mouse wake up events as well as pme support. the pcc supports multiple low power-down modes. the lpc47m172 is acpi 1.0b/2.0 compatible. the motherboard glue logic includes various power management logic; including generation of nrsmrst, power ok signal generation, 5v main and standby reference generation. there are also three leds to indicate power status and hard drive activity. the translation circuit converts 3.3v signals to 5v signals. also included is smbus main power we ll to resume power well isolation circuitry. the lpc47m172 s upports the isa plug-and-play standard register set (version 1.0a). the i/o address, dma channel and hardware irq of each logical device in the lpc47m172 may be reprogrammed through the internal configuration register s. there are up to 480 (960 fo r parallel port) i/o address location options, a serialized irq interface, and three dma ch annels. on chip, interrupt generating registers enable external software to generate irq1 through irq15 on the serial irq interface. the lpc47m172?s enhanced digital data separator do es not require any exter nal filter components and is therefore easy to use and offers lower system costs and reduced board area. the lpc47m172 is register compatible with smsc?s proprietary 82077aa core. this device utilizes two selectable (see chapter 2) re gister sets; (1) standard smsc and (2) tailored for intel reference designs. these register sets are detailed in chapter 6 (section 6.1).
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 12 smsc lpc47m172 datasheet chapter 2 pin layout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 lpc47m172 128 pin qfp mclk mdat kclk kdat ga20m vcc nkbdrst vss ndskchg nhdsel nrdata nwrtprt ntrk0 nwgate nwdata nstep ndir nds0 nmtr0 nindex drvden1 drvden0 ndcd ndsr rxd nrts txd ncts vss ndtr (xor) vcc nri slct pe busy nack pd7 pd6 irtx2 irrx2 ndcd2 ndtr2 ncts2 vcc nrts2 ndsr2 txd2 rxd2 nri2 nc/vtr (note) ddcsda_5v/gp20 ddcsda_3v/gp22 ddcscl_5v/gp21 ddcscl_3v/gp23 gp17/fan_tach2 gp16/fan_tach1 vss gp15 gp14 vtr gp13 gp12 gp11 gp10 ncdc_dwn_rst ncdc_dwn_enab/gp24 naud_link_rst nio_pme test_en f_cap vss ylw_led grn_led vtr nrsmrst clocki32 smb_dat_r smb_dat_m smb_clk_r smb_clk_m nslp_s5 nslp_s3 pwrgd_3v ncpu_present pwrgd_ps nps_on sck_bjt_gate latched_bf_cut vss nbackfeed_cut vtr nfprst npcirst_out2 npcirst_out ref5v_stby v_5p0_stby ref5v nscsi nsecondary_hd nprimary_hd nhd_led clocki pd5 pd4 pd3 pd2 pd1 pd0 nerror vss nslctin ninitp vcc nalf nstrobe nlpcpd ser_irq nldrq pci_clk nlframe lad3 vss lad2 vcc lad1 lad0 npci_reset nide_rstdrv figure 2.1 - lpc47m172 pin layout
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 13 smsc lpc47m172 datasheet note: pin 117 is used to select the mode of the logical devic e numbering. this pin affe cts the ld_num bit in the test 7 register (configuration regi ster 0x29), which is used to sele ct logical device numbering in the lpc47m172. see table 6.1 - super i/o block logical device number and addres ses. the pin functions as follows: ? the pin has an internal pull-down resistor that sele cts the non-standard smsc (i ntel compatible) mode. to select this mode, the pin should be left unconnected. this configuration clears the ld_num bit to ?0? and the associated functionality corresponds to the existing functionality in the part when the ld_num bit=0. ? connecting this pin to vtr will select the standar d smsc mode of the logica l device numbering. this configuration sets the ld_num bit to ?1? and the associated functionality corresp onds to the existing functionality in the part when the ld_num bit=1.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 14 smsc lpc47m172 datasheet chapter 3 description of pin functions table 3.1 - lpc47m172 pin description pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes power and ground pins (20) see note 11 6,31, 49,60, 123 vcc +3.3 volt main supply voltage (5) pwr 76,93, 107, 117 see note vtr +3.3 volt standby supply voltage (4) see note pwr 11 71 v_5p0_stby +5 volt standby supply voltage. pwr 8,29, 46,58, 78,96, 110 vss gr ound (7) pwr 70 ref5v 5v reference output. requires external pull-up to vcc5v. ao vcc 72 ref5v_stby highest system standby voltage. requires external pull-up to v_5p0_stby. ao vtr 97 f_cap internal regulator filt er capacitor. this pin is a no connect. a filter capacitor can be placed on this pin if it is required by system board layout. clocks (2) 65 clocki 14.318mhz clock input is vcc 91 clocki32 32.768khz clock input is vtr 4 processor/host lpc interface (11) 52 nlpcpd active low input power down signal indicates that the lpc47m172 should prepare for power to be shut-off on the lpc interface. pci_i vcc 5 53 ser_irq serial irq pin used with the pci_clk pin to transfer lpc47m172 interrupts to the host. pci_io vcc 54 nldrq active low output used for encoded dma/bus master request for the lpc interface. pci_o vcc 55 pci_clk 33.33 mhz pci clock input. pci_iclk vcc 56 nlframe active low input indicates start of new cycle and termination of broken cycle. pci_i vcc 57,59, 61,62 lad[3:0] active high lpc i/o used for multiplexed command, address and data bus. pci_io vcc
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 15 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 63 npci_reset active low input used as lpc interface reset. 3.3v and 5v buffered copy of pci reset signal is available on npcirst_out and nide_rstdrv. these pins are listed under glue pins. pci_i vcc 99 nio_pme power management event output. this active low power management event signal allows to request wakeup. this pin can be configured as push-pull output. od8 vtr fdd interface (14) 9 ndskchg this input senses t hat the drive door is open or that the diskette has possibly been changed since the last drive selection. this input is inverted and read via bit 7 of i/o address 3f7h. the ndskchg bit also depends upon the state of the force disk change bits in the force disk change register (see chapter 11 configuration). is vcc 10 nhdsel head select output. this high current output selects the floppy disk side for reading or writing. a logic ?1? on this pin means side 0 will be accessed, while a logic ?0? means side 1 will be accessed. can be configured as an open-drain output. o12 vcc 11 nrdata raw serial bit stream from the disk drive, low active. each falling edge represents a flux transition of the encoded data. is vcc 12 nwrtprt this active low schmitt trigger input senses from the disk drive that a disk is write protected. any write command is ignored. the nwrprt bit also depends upon the state of the force write protect bit in the fdd option register (see the configuration registers section). is vcc 13 ntrk0 this active low schmitt trigger input senses from the disk drive that the head is positioned over the outermost track. is vcc 14 nwgate write gate output. this active low high current driver allows current to flow through the write head. it becomes active just prior to writing to the diskette. can be configured as an open-drain output. o12 vcc 15 nwdata write disk data output. this active low high current driver provides the encoded data to the disk drive. each falling edge causes a flux transition on the media. can be configured as an open-drain output. o12 vcc
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 16 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 16 nstep step pulse output. this active low high current driver issues a low pulse for each track-to-track movement of the head. can be configured as an open-drain output. o12 vcc 17 ndir step direction output. this high current low active output determines the direction of the head movement. a logic ?1? on this pin means outward motion, while a logic ?0? means inward motion. can be configured as an open-drain output. o12 vcc 18 nds0 drive select 0 output. can be configured as an open-drain output. o12 vcc 19 nmtr0 motor on 0 output. can be configured as an open-drain output. o12 vcc 20 nindex this active low schmitt trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. is vcc 21 drvden1 drive density select 1 output. indicates the drive and media selected. can be configured as open-drain output. o12 vcc 22 drvden0 drive density select 0 output. indicates the drive and media selected. can be configured as open-drain output. o12 vcc serial port 1 interface (8) 23 ndcd1 active low data carrier detect input for the serial port. handshake signal that notifies the uart that carrier signal is detected by the modem. the cpu can monitor the status of ndcd signal by reading bit 7 of modem status register (msr). a ndcd signal state change from low to high after the last msr read will set msr bit 3 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when ndcd changes state. note: bit 7 of msr is the complement of ndcd. i vcc 24 ndsr1 active low data set ready input for the serial port. handshake signal that notifies the uart that the modem is ready to establish the communication link. the cpu can monitor the status of ndsr signal by reading bit 5 of modem status register (msr). a ndsr signal state change from low to high after the last msr read will set msr bit 1 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when ndsr changes state. note: bit 5 of msr is the complement of ndsr. i vcc 25 rxd1 receiver serial data input. is vcc
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 17 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 26 nrts1 active low request to send output for the serial port. handshake output signal notifies modem that t he uart is ready to transmit data. this signal can be programmed by writing to bit 1 of the modem control register (mcr). the hardware reset will reset the nrts signal to inactive mode (high). nrts is forced inactive during loop mode operation. o8 vcc 27 txd1 transmit serial data output. o12 vcc 28 ncts1 active low clear to send input for the serial port. handshake signal that notifies the uart that the modem is ready to receive data. the cpu can monitor the status of ncts signal by reading bit 4 of modem status register (msr). a ncts signal state change from low to high after the last msr read will set msr bit 0 to a 1. if bit 3 of the interrupt enable register is set, the interrupt is generated when ncts changes state. the ncts signal has no effect on the transmitter. note: bit 4 of msr is the complement of ncts. i vcc 30 ndtr1 (xor) active low data terminal ready output for the serial port. handshake output signal notifies modem that the uart is ready to establish data communication link. this signal can be programmed by writing to bit 0 of modem control register (mcr). the hardware reset will reset the ndtr signal to inactive mode (high). ndtr is forced inactive during loop mode operation. xor chain output. o8 vcc 32 nri1 active low ring indi cator input for the serial port. handshake signal that notifies the uart that the telephone ring signal is detected by the modem. the cpu can monitor the status of nri signal by reading bit 6 of modem status register (msr). a nri signal state change from low to high after the last msr read will set msr bit 2 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when nri changes state. note: bit 6 of msr is the complement of nri. i vtr 6 serial port 2 interface (8) 118 nri2 active low ring indica tor input for serial port 2. see description for nri1. ipd vtr 6, 10 119 rxd2 receiver serial data input. ispd_400 vcc 120 txd2 transmit serial data output. o12 vcc
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 18 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 121 ndsr2 active low data set ready input for serial port 2. see description for ndsr1. ipd vcc 10 122 nrts2 active low request to send output for serial port 2. see description for nrts1. o8 vcc 124 ncts2 active low clear to s end input for serial port 2. see description for ncts1. ipd vcc 10 125 ndtr2 active low data terminal ready output for serial port 2. see description for ndtr1. o8 vcc 126 ndcd2 active low data carrier detect input for serial port 2. see description for ndcd1. ipd vcc 10 infrared interface (2) 127 irrx2 infrared receive input. ispd_400 vcc 10 128 irtx2 infrared transmit output. o12 vcc 9 parallel port interface (17) 33 slct this high active input from the printer indicates that it has power on. bit 4 of the printer status register reads the slct input. refer to para llel port description for use of this pin in ecp and epp mode. i vcc 34 pe another status input from the printer, a high indicating that the printer is out of paper. bit 5 of the printer status register reads the pe input. refer to parallel port description for use of this pin in ecp and epp mode. i vcc 35 busy this is a status input from the printer, a high indicating that the printer is not ready to receive new data. bit 7 of the printer status register is t he complement of the busy input. refer to parallel port description for use of this pin in ecp and epp mode. i vcc 36 nack a low active input from the printer indicating that it has received the data and is ready to accept new data. bit 6 of the printer status register reads the nack input. refer to parallel port description for use of this pin in ecp and epp mode. i vcc 37 pd7 port data 7 i/o iop14 vcc 38 pd6 port data 6 i/o iop14 vcc 39 pd5 port data 5 i/o iop14 vcc 40 pd4 port data 4 i/o iop14 vcc 41 pd3 port data 3 i/o iop14 vcc 42 pd2 port data 2 i/o iop14 vcc 43 pd1 port data 1 i/o iop14 vcc 44 pd0 port data 0 i/o iop14 vcc
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 19 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 45 nerror a low on this input from the printer indicates that there is an error condition at the printer. bit 3 of the printer status register reads the nerr input. refer to parallel port description for use of this pin in ecp and epp mode. i vcc 47 nslctin this active low output selects the printer. this is the complement of bit 3 of the printer control register. refer to parallel port description for use of this pin in ecp and epp mode. can be configured as an open-drain output. op14 vcc 48 ninitp this output is bit 2 of the printer control register. this is used to initiate the printer when low. refer to parallel port description for use of this pin in ecp and epp mode. can be configured as an open-drain output. op14 vcc 50 nalf this output goes low to cause the printer to automatically feed one line after each line is printed. the nalf output is the complement of bit 1 of the printer control register. refer to parallel port description for use of this pin in ecp and epp mode. can be configured as an open-drain output. op14 vcc 51 nstrobe an active low pulse on this output is used to strobe the printer data into the printer. the nstrobe output is the complement of bit 0 of the printer control register. refer to parallel port description for use of this pin in ecp and epp mode. can be configured as an open-drain output. op14 vcc keyboard/mouse interface (6) 1 mclk mouse clock i/o iod24 vcc 2 mdat mouse data i/o iod24 vcc 6 3 kclk keyboard clock i/o iod24 vcc 4 kdat keyboard data i/o iod24 vcc 6 5 ga20m gate a20 open-drain output od8 vcc 7 7 nkbdrst keyboard reset open-drain output od8 vcc 7 glue pins (29) 64 nide_rstdrv ide reset output od8 vcc 3 66 nhd_led hard drive front panel led open-drain output od12 vcc 3 67 nprimary_ hd ide primary drive active input ispu_400 vcc 68 nsecondary _hd ide secondary drive active input ispu_400 vcc 69 nscsi scsi drive active input ispu_400 vcc
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 20 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 73 npcirst_out buffered pci reset output op14 vtr 74 npcirst_out 2 second buffered pci re set output op14 vtr 75 nfprst reset input from front panel ispu_400 vtr 77 nbackfeed_ cut open-drain output used for str circuitry od8 vtr 3 79 latched_bf_ cut latched backfeed cut output for str circuitry op14 vtr 80 sck_bjt_ gate open-drain gate output for the sck_bjt in suspend-to-ram od8 vtr 3 81 nps_on power supply turn-on open drain output od8 vtr 3 82 pwrgd_ps power good input from power supply ispu_400 vtr 83 ncpu_present cpu present input from processor ispu_400 vtr 84 pwrgd_3v power good output o8 vtr 85 nslp_s3 s3 power state input from south bridge is_400 vtr 86 nslp_s5 input from south bridge for transitioning to the s5 power state is_400 vtr 87 smb_clk_m smbus clock main io_sw vtr 88 smb_clk_r smbus clock resume io_sw vtr 89 smb_dat_m smbus data main io_sw vtr 90 smb_dat_r smbus data resume io_sw vtr 92 nrsmrst resume reset output o8 vtr 100 naud_link_ rst ac97 link reset input i vtr 101 ncdc_dwn_ enab/gp24 ac97 codec down enable input. general purpose i/o. gpio can be configured as an open-drain output. io12 vtr 6 102 ncdc_dwn_ rst ac97 codec down reset output. o12 vtr 113 ddcscl_3v/ gp23 3.3v ddc clock general purpose i/o. gpio can be configured as an open-drain output. io_sw/is od8 vtr 3, 6, 8 114 ddcscl_5v/ gp21 5v ddc clock general purpose i/o. gpio can be configured as an open-drain output. io_sw/is od8 vtr 3, 6, 8 115 ddcsda_3v/ gp22 3.3v ddc data general purpose i/o. gpio can be configured as an open-drain output. io_sw/is od8 vtr 3, 6, 8 116 ddcsda_5v/ gp20 5v ddc data general purpose i/o. gpio can be configured as an open-drain output. io_sw/is od8 vtr 3, 6, 8 power leds (2) 94 grn_led green power led open-drain output od24 vtr 95 ylw_led yellow power led open-drain output od24 vtr general purpose i/o (8) 103- 105 gp10-gp12 general purpose i/o. gpio can be configured as an open-drain output. iso8 vtr 6
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 21 smsc lpc47m172 datasheet pin# name (note 1) description buffer name (note 2) pwr well (note 3) notes 106, 108, 109 gp13-gp15 general purpose i/o. gpio can be configured as an open-drain output. io8 vtr 6 111 gp16/ fan_tach1 general purpose i/o. gpio can be configured as an open-drain output. fan tachometer 1 input io8 vtr 6 112 gp17/ fan_tach2 general purpose i/o. gpio can be configured as an open-drain output. fan tachometer 2 input io8 vtr 6 test (1) 98 test_en test enable input for xor-chain test ? the external pull-up or internal pull-down sets the strap value. the xor output is the ndtr1 pin. ipd vtr no connect (1) see note11 117 nc no connect ipd - 11 note 1: the ?n? as the first letter of a signal name or the ?#? as the suffix of a signal name indicates an ?active low? signal. the primary and secondary functi ons on the pins are separated by ?/?. note 2 : the buffer names are described in the ?buffer name descriptions? section. note 3: open-drain pins should be pulled-up externally to supply shown in the power well column. the nide_rstdrv, nhd_led, ddcsda_5v and ddcscl_5v op en-drain pins require external pull-ups to vcc5v. the nbackfeed_cut, sck_bjt_gate and n ps_on open-drain pins require external pull- ups to v_5p0_stby. inputs with internal pull-ups are pulled internally to the supply shown in the power well column. all other pins are driven under the power we ll shown. see the ?pins with internal resistors?, ?pins that require external resistors? and ?default state of pins? sections. note 4: the 32.768 khz input clock must not be driven high when vtr = 0v. clocki32 is clock source to various logic in the part, including led, ?wake on specific key? and nfprst debounce circuitry. the 32 khz input clock must always be connected. there is a bit in t he configuration register at 0xf0 in logical device a that indicates whether or not the 32khz clock is con nected. this bit determines the clock source for the logic. this bit must always be set to ?0? (?0?=32 khz clock connected; reset default=?0?). note 5: the nlpcpd pin may be tied high. the lpc interf ace will function properly if the npci_reset signal follows the protocol defined for the nlreset signal in the ?low pin count interface specification?. however, if nlpcpd is tied high, the keyb oard wakeup isolation logic will be affected. note 6: these pins (except ddc and fan_tach functions) are also inputs to vtr powered logic internal to the part. if ddc and fan_tach functions are selected on gpios, the pins will tri-state when vcc power is removed. note 7: external pullups must be placed on the nkbdrst and ga20m pins. if the nkbdrst and ga20m functions are to be used, the system must ensure that these pins are high. see the ?that require external resistors? section. note 8 : when ddc functions are selected on gp20-gp23, the pins become io_sw type and require external pull- ups to the appropriate voltages. see the ?that requi re external resistors? section. when the gpio functions are selected, the pins are is0d8. note 9: the irtx2 pin is driven low upon power-up of vcc. this pin will remain low following a power-up (vcc por) until it is selected via the ir mux bits and serial port 2 is enabled by setting the activate bit, at which
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 22 smsc lpc47m172 datasheet time the pin will reflect the state of the transmit output of the serial port 2 block. this is a vcc powered pin. note 10: these pins are internally pulled down to vss only until serial port 2 is enabled. once serial port 2 is enabled, the pull-downs are removed until vtr por. note 11: pin 117 is used to select the mode of the logical device numbering. this pin affects the ld_num bit in the test 7 register (configuration regi ster 0x29), which is used to select logical device numbering in the lpc47m172. see table 6.1 - super i/o block logical device number and addresses. the pin has an internal pull-down resistor that selects the non-smsc (intel compatible) mode. to select this mode, the pin should be left unconnected. connecting this pin to vtr will select the smsc mode of the logical device numbering. 3.1 buffer name descriptions note: refer to the ?electrical characteristics? section. pwr power and ground i input ttl compatible. ipu input with 30ua integrated pull-up ipd input with 30ua integrated pull-down is input with 250mv schmitt trigger. is_400 input with 400mv schmitt trigger. ispu_400 input with 400mv schmitt tr igger and 30ua integrated pull-up. ispd_400 input with 400mv schmitt tri gger and 30ua integrated pull-down. o8 output, 8ma sink, 4ma source. od8 output (open drain), 8ma sink. o12 output, 12ma sink, 6ma source. od12 output (open drain), 12ma sink. op14 output, 14ma sink, 14ma source. od24 output (open drain), 24ma sink. ao output ? analog with 5v level io8 input/output, 8ma sink, 4ma source. iso8 input with 250mv schmitt trigger /output, 8ma sink, 4ma source. isod8 input with 250mv schmitt trigger, low leakage/output (open-drain), 8ma sink. io12 input with schmitt trigger/output, 12ma sink, 6ma source. iop14 input/output, 14ma sink, 14ma source. iod24 input/output (open drain), 24ma sink. io_sw input/output, special type. pins of this type are connected in pairs thro ugh a switch. the switch provides a 25 ohm (max) resistance to ground when closed. pci_io input/output. these pins meet the pci 3.3v ac and dc characteristics. (note 1) pci_o output. these pins meet the pci 3.3v ac and dc characteristics. (note 1) pci_i input. these pins meet the pci 3. 3v ac and dc characteristics. (note 1) pci_iclk clock input. these pins meet the pci 3.3v ac and dc characteristics and timing. (note 2) note 1: see the ?pci local bus specificat ion,? revision 2.1, section 4.2.2. note 2: see the ?pci local bus specification,? revision 2.1, secti on 4.2.2 and 4.2.3.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 23 smsc lpc47m172 datasheet 3.2 pins with internal resistors the following pins have internal resistors: table 3.2 - pins with internal resistors signal name resistor value notes ncpu_present 30ua pull-up to vtr nfprst 30ua pull-up to vtr nprimary_hd 30ua pull-up to vcc pwrgd_ps 30ua pull-up to vtr nscsi 30ua pull-up to vcc nsecondary_hd 30ua pull-up to vcc test_en 30ua pull-down to vss 3.3 pins that require external resistors the following pins require external resistors: table 3.3 - pins that require external resistors signal name resistor value notes ser_irq 10 kohm pull-up to vcc nldrq 100 kohm pull-up to vcc lad[3:0] 100 kohm pull-up to vcc mclk mdat kclk kdat 2.7 kohm pull-up to vreg_ps2. the vreg_ps2 is the voltage regulator for the ps/2 ports. ga20m 10 kohm pull-up to vcc kbdrst 10 kohm pull-up to vcc nio_pme 10 kohm pull-up to vtr nhdsel 10 kohm nwgate 10 kohm nwdata 10 kohm nstep 10 kohm ndir 10 kohm nds0 10 kohm nmtr0 10 kohm drvden1 10 kohm drvden0 10 kohm pull-up required if used as open-drain output. pull-up to vcc. ndskchg 1 kohm pull-up to vcc nrdata 1 kohm pull-up to vcc nwrtprt 1 kohm pull-up to vcc ntrk0 1 kohm pull-up to vcc nindex 10 kohm pull-up to vcc ref5v 1 kohm pull-up to vcc5v ref5v_stby 1 kohm pull-up to v_5p0_stby
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 24 smsc lpc47m172 datasheet signal name resistor value notes nide_rstdrv 1 kohm pull-up to vcc5v nps_on 1 kohm pull-up to v_5p0_stby nbackfeed_cut 1 kohm pull-up to v_5p0_stby sck_bjt_gate 1 kohm pull-up to v_5p0_stby ncdc_dwn_enab 10 kohm pull-down to vss ylw_led 220 ohm pull-up to vtr nhd_led 330 ohm pull-up to vcc ddcsda_3v 4.7 kohm pull-up to vcc ddcscl_3v 4.7 kohm pull-up to vcc ddcsda_5v 2.2 kohm pull-up to vcc5v ddcscl_5v 2.2 kohm pull-up to vcc5v smb_clk_m 2.7 kohm pull-up to vcc smb_clk_r 2.7 kohm pull-up to vtr smb_dat_m 2.7 kohm pull-up to vcc smb_dat_r 2.7 kohm pull-up to vtr grn_led 220 ohm pull-up to vtr gpios design-dependant pull-up to appropriate voltage (not to exceed 5v) 3.4 default state of pins the following table shows the default state of pins. notes: ? off the pin is not powered by suspend supply and is valid under main power only. ? hi-z the pin is powered, but tri-stated ei ther because the pin is open-drain or vcc function is selected on vtr powered pin. the pin requires external pull-up when tri-stated. ? active the pin is powered and active high. ? running the input clock is powered and running. ? input the pin is powered and driven by external circuitry to high or low level. ? out the pin is powered and driven to high or low level by the part. the input or output configur ation state of the pin is retained and is not affected by pci reset or vcc por.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 25 smsc lpc47m172 datasheet table 3.4 - default state of pins signal name pwr well pci reset vcc por vtr por notes ref5v_stby vtr - - active this pin requires external pull- up to v_5p0_stby ref5v vcc active active off this pin requires external pull- up to vcc5v clocki vcc running running off clocki32 vtr running running running nio_pme vtr - - hi-z pci_clk vcc input input off nlpcpd vcc input input off npci_reset vcc input input off ser_irq vcc input input off nldrq vcc input input off nlframe vcc input input off lad[0:3] vcc input input off ndskchg vcc input input off nhdsel vcc out ? low out ? low off nrdata vcc input input off nwrtprt vcc input input off ntrk0 vcc input input off nwgate vcc hi-z hi-z off nwdata vcc hi-z hi-z off nstep vcc out ? low out ? low off ndir vcc out ? low out ? low off nds0 vcc hi-z hi-z off nmtr0 vcc hi-z hi-z off nindex vcc input input off drvden0 vcc out ? high out ? high off drvden1 vcc out ? high out ? high off ndcd1 vcc input input off ndsr1 vcc input input off rxd1 vcc input input off nrts1 vcc out ? high out ? high off txd1 vcc out ? low out ? low off ncts1 vcc input input off ndtr1 (xor) vcc out ? high out ? high off nri1 vtr - - input ndcd2 vcc input input off this pin is internally pulled down to vss until serial port 2 is enabled. ndsr2 vcc input input off this pin is internally pulled down to vss until serial port 2 is enabled. rxd2 vcc input input off this pin is internally pulled down to vss until serial port 2 is enabled. nrts2 vcc out ? high out ? high off txd2 vcc out ? low out ? low off
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 26 smsc lpc47m172 datasheet signal name pwr well pci reset vcc por vtr por notes ncts2 vcc input input off this pin is internally pulled down to vss until serial port 2 is enabled. ndtr2 vcc out ? high out ? high off nri2 vtr - - input this pin is internally pulled down to vss until serial port 2 is enabled. irrx2 vcc input input off this pin is internally pulled down to vss until serial port 2 is enabled. irtx2 vcc out ? low out ? low off slct vcc input input off pe vcc input input off busy vcc input input off nack vcc input input off pd[7:0] vcc input input off error vcc input input off nslctin vcc out ? high out ? high off ninitp vcc out ? high out ? high off nalf vcc out ? high out ? high off nstrobe vcc out ? high out ? high off mclk vcc hi-z hi-z off mdat vcc - - input kclk vcc hi-z hi-z off kdat vcc - - input ga20m vcc hi-z hi-z off nkbdrst vcc hi-z hi-z off naud_link_rst vtr - - input ncdc_dwn_enab/ gp24 vtr - - input ncdc_dwn_rst vtr - - out ? low nfprst vtr - - input this pin is pulled up internally nbackfeed_cut vtr - - hi-z this pin requires external pull- up to v_5p0_stby. latched_bf_cut vtr - - out ? low sck_bjt_gate vtr - - hi-z this pin requires external pull- up to v_5p0_stby. nscsi vcc input input off this pin is pulled up internally grn_led vtr - - out ? low ylw_led vtr - - out ? low nhd_led vcc hi-z hi-z off nsecondary_hd vcc input input off this pin is pulled up internally nprimary_hd vcc input input off this pin is pulled up internally nide_rstdrv vcc out ? low out ? low off requires external pull-up to vcc5v pwrgd_ps vtr - - input nps_on vtr - - hi-z requires external pull-up to v_5p0_stby ncpu_present vtr - - input this pin is pulled up internally
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 27 smsc lpc47m172 datasheet signal name pwr well pci reset vcc por vtr por notes nslp_s3 vtr - - input nslp_s5 vtr - - input nrsmrst vtr - - out ? low pwrgd_3v vtr - - out ? low npcirst_out vtr out ? low out ? low out ? low npcirst_out2 vtr out ? low out ? low out ? low gp10-gp15 vtr - - input gp16 - - input fan_tach1 vtr hi-z hi-z hi-z gp17 - - input fan_tach2 vtr hi-z hi-z hi-z the gpio and fan_tach functions are multiplexed on the same pin with gpio as the default function. smb_clk_m vtr hi-z hi-z hi-z smb_clk_r vtr - - hi-z smb_dat_m vtr hi-z hi-z hi-z smb_dat_r vtr - - hi-z ddcsda_5v hi-z hi-z hi-z gp20 vtr - - hi-z ddcscl_5v hi-z hi-z hi-z gp21 vtr - - hi-z the ddc and gpio functions are multiplexed on the same pin with ddc as the default function. ddc function requires external pull-up to vcc5v. ddcsda_3v hi-z hi-z hi-z gp22 vtr - - hi-z ddcscl_3v hi-z hi-z hi-z gp23 vtr - - hi-z the ddc and gpio functions are multiplexed on the same pin with ddc as the default function. ddc function requires external pull-up to vcc. test_en vtr - - input test mode pin. this pin has internally pull-down to vss. external pull-up required to enable the test mode.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 28 smsc lpc47m172 datasheet chapter 4 block diagram ylw_led grn_led lpc47m172 (128 qfp) digital data separator with write precom- pensation smsc proprietary 82077 compatible vertical floppydisk controller core wdata wclock rclock rdata fan monitoring power led multi-mode parallel port with chiprotect tm pd[7:0] busy, slct, pe, nerror, nack nstrobe, ninitp, nslctin, nalf fan_tach2* fan_tach1* internal bus (data, address, and control lines) high-speed 16550a uart port rxd ndsr nri ncts nio_pme gpios gp10-gp15, gp16*, gp17* (gp20-gp23)* nwdata ndir, nstep, nds0, nmtr0 ntrk0, ndskchg, nindex, nwrtprt drvden0, drvden1 nwgate, nhdsel lad[3:0] nlframe nldrq npci_reset nlpcpd ser_irq pci_clk lpc bus interface serial irq / interrupt generating registers test_en xor-chain kclk, mclk kdat, mdat ga20m nkbdrst clocki nfprst nsecondary_hd npci_rst_out npci_rst_out2 f_cap v_5p0_stby nrsmrst ref5v ref5v_stby naud_link_rst ncdc_dwn_enab* ncdc_dwn_rst nhd_led nscsi nide_rstdrv nprimary_hd pwrgd_3v nslp_s3 nslp_s5 smb_clk_m note 1: this diagram shows the various functions available on the chip (not pin layout). the block diagram should not be used for pin count. note 2: functions with asterisks (*) are located on multifunctional pins. pme / power control clocki32 latched_bf_cut nps_on sck_bjt_gate nbackfeed_cut ddcsda_3v* ddcscl_3v* smb_dat_m smb_dat_r ddcsda_5v* ddcscl_5v* pwrgd_ps ncpu_present smb_clk_r txd nrts ndtr* ndcd nrdata npci_reset nslp_s5 cnr logic hard drive front panel led power sequencing vga voltage translation xor* smbus isolation clock gen configuration registers keyboard/mouse 8042 controller vcc (3.3v) vtr (3.3v) v_5p0_stby buffered pci reset gp24* resume reset generation 5v reference generation high-speed 16550a uart port 2 w/ infrared ndsr2 nri2 ncts2 nrts2 ndcd2 rxd2 txd2 ndtr2 irtx2 irrx2 figure 4.1 - lpc47m172 block diagram
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 29 smsc lpc47m172 datasheet chapter 5 power and clock functionality the lpc47m172 has three power planes: vcc, vtr and v5p0_stby. 5.1 3 volt operation / 5 volt tolerance the lpc47m172 is a 3.3 volt part. it is intended sole ly for 3.3v applications. non-lpc bus pins are 5v tolerant; that is, the oper ating input voltage is 5. 5v max, and the i/o buffer output pads are backdrive protected (they do not impose a load on any external vcc powered circuitry). the lpc interface pins are 3.3 v only. these signals meet pci dc specifications for 3.3v signaling. the nrsmrst pin is also 3.3v only. the following lists the pins that are 3.3v only (not 5v tolerant): ? lad[3:0] ? nlframe ? nldrq ? nlpcpd ? nrsmrst the input voltage for all other pins is 5.5v max. these pins include a ll non-lpc bus pins and the following pins: ? npci_reset ? pci_clk ? ser_irq ? nio_pme 5.2 vcc power the lpc47m172 is a 3.3 volt part. the vcc supply is 3.3 volts (nominal). see the ?operational description? section and the ?maximum current values? subsection. 5.3 vtr power the lpc47m172 requires a trickle supply (vtr) to provide sleep current for the programmable wake-up events in the pme interface and other suspend state logic when vcc is removed. the vtr supply is 3.3 volts (nominal). see the operational description se ction. the maximum vtr current that is required depends on the functions that are used in the part. see trickle power functionality subsection and maximum current values subsection. if the lpc47m172 is not intended to provide wake-up and/or suspend power capabilities on standby current, vtr can be connected to vcc. the vtr pin generates a vtr power-on-reset signal to initialize these components. note: if vtr is to be used for programmable wake-up events when vcc is removed, vtr must be at its full minimum potential at least 10 s before vcc begins a power-on cycle. when vtr and vcc are fully powered, the potential difference between the two supplies must not exceed 500mv.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 30 smsc lpc47m172 datasheet 5.3.1 trickle power functionality when the lpc47m172 is running under vtr only (vcc removed), pme wakeup events are active and (if enabled) able to assert the nio_pme pin active low. the following lists the wakeup events: ? uart1 and uart 2 ring indicator ? keyboard data ? mouse data ? ?wake on specific key? logic ? gpios for wakeup. see below. the following requirements apply to all i/o pins that are specified to be 5 volt tolerant. i/o buffers that are wake-up event compatible are powered by vcc. under vtr power (vcc=0), these pins may only be configured as i nputs. these pins have input buffers into the wakeup logic that are powered by vtr. i/o buffers that may be configured as either push-pull or open drain under vtr power (vcc=0), are powered by vtr. this means, at a minimum, they w ill source their specified current from vtr even when vcc is present. the gpios that are used for pme wakeup as input are gp10-gp17 and gp20-gp23 buffers are powered by vtr. these pins have input buffers into the wakeup logic that are powered by vtr. gp24 does not have input buffer into the wakeup logic. the output buffer of gp24 is by vtr but does this pin does not have an input buffer into wakeup logic powered by vtr. for blocks, registers and pins that are powe red by vtr see table 3.1 and figure 4.1. 5.4 v5p0_stby power the v5p0_stby pin is used in nrsmrst generation ci rcuit. the v5p0_stby, however, does not power the nrsmrst pad. 5.5 32.768 khz trickle clock input the lpc47m172 utilizes a 32.768 khz trickle input to supply a clock signal for the nfprst debounce circuitry, led blink and wake on specific key function. 5.5.1 indication of 32khz clock there is a bit to indicate whether or not the 32khz cl ock input is connected to the lpc47m172. this bit is located at bit 0 of the clocki32 conf iguration register at 0xf0 in logical device a (see table 11.14). this register is powered by vtr and reset on a vtr por. bit[0] (clk32_prsn) is defined as follows: 0=32khz clock is connected to the clki32 pin (default) 1=32khz clock is not connected to the clki32 pin (pin is grounded).
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 31 smsc lpc47m172 datasheet bit 0 controls the source of the 32khz (nominal) cl ock for the nfprst debounce circuitry, the led blink logic and the ?wake on specific key? logic. when the external 32khz clock is connected, that will be the source for the nfprst debounce circuitry, led and ?wake on specific key? logic. when the external 32khz clock is not connected, an internal 32khz clock source will be derived from the 14mhz clock for the ?wake on specific key? logic. the nfprst debounce circuitry and led require the 32khz clock be always connected. the ?wake on specific key? function will not work un der vtr power (vcc removed) if the external 32khz clock is not connected. it will work under vcc power even if the external 32 khz clock is not connected. 5.6 14.318 mhz clock input the lpc47m172 utilizes a 14.318 mhz clock input (clo cki). this clock is used to generate specific clocks needed for various logic (including sio functi ons, fan tachometer, etc.) in the lpc47m172. the clocki is powered by vcc and is not available in vtr power only (vcc=0). 5.7 internal pwrgood an internal pwrgood logical control is included to minimize the effect s of pin-state uncertainty in the host interface as vcc cycles on and off. when the internal pwrgood signal is ?1? (active), vcc > 2.3v (nominal), and the lpc47m172 host interface is active. when the internal pwrgood signal is ?0? (inactive), vcc <= 2.3v (nominal), and the lpc47m172 host interface is inactive; that is, lpc bus reads and writes will not be decoded. the lpc47m172 device pins nio_pme, clocki32, kd at, mdat, nri1, nri2, and most gpios (as input) are part of the pme interface and remain active wh en the internal pwrgood signal has gone inactive, provided vtr is powered. other vtr powered pins listed in table 3.1 also remain active when the internal pwrgood signal has gone inactive, provided vtr is powered. see trickle power functionality section. 5.8 maximum current values see the ?operational description? sect ion for the maximum current values. the maximum vtr current, i tr , is given with all outputs open (not loaded), and all inputs transitioning from/to 0v to/from 3.3v. the total maximum current for the part is the unloaded value plus the maximum current sourced by the pin that is driven by vtr. t he pins that are powered by vtr are listed in the table 3.1. the push-pull capable outputs will source minimu m current specified in table 12.2 at 2.4v when driving. the maximum vcc current, i cc , is given with all outputs open (not loaded) and all inputs transitioning from/to 0v to/from 3.3v. 5.9 power management events (pme/sci) the lpc47m172 offers support for power management events (pmes), also referred to as system control interrupt (sci) events. the terms pme and sc i are used synonymously throughout this document to refer to the indica tion of an event to the chipset via the assertion of the nio_pme output signal. see the ?pme support? section.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 32 smsc lpc47m172 datasheet chapter 6 functional description the following sections describe the functional blocks located in the lpc47m172 (see figure 4.1). the various super i/o components are described in the foll owing sections and their registers are implemented as typical plug-and-play components (see section chapter 11 ? configuration on page 172). 6.1 super i/o registers table 6.1 shows the logical device number and addresses of fdc, serial and parallel ports, keyboard/mouse, power control and gpio block, runtim e register block and configuration register block of the super i/o immediately after power up. the logi cal device numbering is cont rolled by the ld_num bit in the test 7 configuration register (0x29). the state of ld_num is determined by pin 117 as described in chapter 2. the base addresses of the blocks can be programmed via the configuration registers. some addresses are used to access more than one register. refer to the ?configuration? section for configuration register description. table 6.1 - super i/o block logical device number and addresses ld_num bit = 0 (default) (non-standard smsc register sets) ld_num bit = 1 (standard smsc register sets) ld number device name block address ld number device name block address 00h floppy disk controller base+(0-5) and +(7) 00h floppy disk controller base+(0-5) and +(7) 01h parallel port base+(0-3) base+(0-7) base+(0-3), +(400-402) base+(0-7), +(400-402) 01h - - 02h serial port 2 base+(0-7) 02h serial port 2 base+(0-7) 03h serial port 1 base+(0-7) 03h parallel port base+(0-3) base+(0-7) base+(0-3), +(400-402) base+(0-7), +(400-402) 04h power control base+(0-31) 04h serial port 1 base+(0-7) 05h mouse 05h - - 06h keyboard 60, 64 06h - - 07h gpio base+(0-31) 07h keyboard/ mouse 60, 64 08h - - 08h - - 09h - - 09h - - 0ah - - 0ah runtime register block ? contains power control and gpio block registers in this mode. base+(0-63) - configuration base + (0-1) - configuration base + (0-1)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 33 smsc lpc47m172 datasheet 6.2 host processor interface (lpc) the host processor communicates with the lpc47m172 through a series of read/write registers via the lpc interface. the port addresses for these register s are shown in table 6.1. register access is accomplished through i/o cycles or dma tran sfers. all registers are 8 bits wide. 6.3 lpc interface the following sub-sections specify th e implementation of the lpc bus. 6.3.1 lpc interface signal definition the signals required for the lpc bus interface are described in the table below. lpc bus signals use pci 33mhz electrical signal characteristics. signal name type description lad[3:0] i/o lpc address/data bus. mult iplexed command, address and data bus. nlframe input frame signal. indicates start of new cycle and termination of broken cycle npci_reset input pci reset. used as lpc interface reset. nldrq output encoded dma/bus master request for the lpc interface. nio_pme od power mgt event signal. allows the lpc47m172 to request wakeup. nlpcpd input powerdown signal. indicates that the lpc4 7m172 should prepare for power to be shut on the lpc interface. ser_irq i/o serial irq. pci_clk input pci clock. note: the clkrun# signal is not implemented in this part. 6.3.2 lpc cycles the following cycle types are supported by the lpc protocol. cycle type transfer size i/o write 1 byte i/o read 1 byte dma write 1 byte dma read 1 byte lpc47m172 ignores cycles that it does not support. 6.3.3 field definitions the data transfers are based on spec ific fields that are used in va rious combinations, depending on the cycle type. these fields are driven onto the lad[3:0] signal lines to communicate address, control and data information over the lpc bus betwe en the host and the lpc47m172. see the low pin count (lpc) interface specification revision 1.0 from intel, section 4.2 for definition of these fields.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 34 smsc lpc47m172 datasheet 6.3.4 nlframe usage nlframe is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. this signal is to be used by the lpc47m172 to know when to monitor the bus for a cycle. this signal is used as a general notific ation that the lad[3:0] lines contain information relative to the start or stop of a cycle, and that the lpc47m172 monitors the bus to determine whether the cycle is intended for it. the use of nlframe allows the lpc47m172 to enter a lower power state internally. there is no need for the lpc47m172 to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. when the lpc47m172 samples nlframe active, it imm ediately stops driving the lad[3:0] signal lines on the next clock and monitor the bus for new cycle information. the nlframe signal functions as described in the low pin count (lpc) interface specification, revision 1.0. 6.3.5 i/o read and write cycles the lpc47m172 is the target for i/o cycles. i/o cycl es are initiated by the host for register or fifo accesses, and will generally have minimal sync time s. the minimum number of wait-states between bytes is 1. epp cycles will depend on the speed of the external device, and may have much longer sync times. data transfers are assumed to be exactly 1-byte. if the cpu requested a 16 or 32- bit transfer, the host will break it up into 8-bit transfers. see the ?low pin count (lpc) interface specification? reference, section 5.2, fo r the sequence of cycles for the i/o read and write cycles. 6.3.6 dma read and write cycles dma read cycles involve the transfer of data from the host (main memory) to the lpc47m172. dma write cycles involve the transfer of data from the lpc47m172 to the host (main memory). data will be coming from or going to a fifo and will have minimal sync ti mes. data transfers to/from the lpc47m172 are 1, 2 or 4 bytes. see the ?low pin count (lpc) interfac e specification? reference, section 6.4, for the field definitions and the sequence of the dma read and write cycles. 6.3.7 dma protocol dma on the lpc bus is handled through the use of the nldrq lines from the lpc47m172 and special encodings on lad[3:0] from the host. the dma mechanism for the lpc bus is described in t he ?low pin count (lpc) interface specification,? revision 1.0.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 35 smsc lpc47m172 datasheet 6.3.8 power management clockrun protocol the clkrun# pin is not implemented in the lpc47m172. see the ?low pin count (lpc) interface sp ecification? revision 1.0, section 8.1. lpcpd protocol see the ?low pin count (lpc) interface sp ecification? revision 1.0, section 8.2. 6.3.9 sync protocol see the ?low pin count (lpc) interface specification? revision 1.0, section 4.2. 1.8 for a table of valid sync values. typical usage the sync pattern is used to add wait states. for read cycles, the lpc47m172 immediately drives the sync pattern upon recognizing the cycle. the host immedi ately drives the sync pattern for write cycles. if the lpc47m172 needs to assert wait states, it does so by driving 01 01 or 0110 on lad[3:0] until it is ready, at which point it will driv e 0000 or 1001. the lpc47m172 will choose to assert 0101 or 0110, but not switch between the two patterns. the data (or wait state sync) will immediately follow the 0000 or 1001 value. the sync value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. the lpc47m172 uses a sync of 0101 for all wait states in a dma transfer. the sync value of 0110 is intended to be used where the number of wait states is large. this is provided for epp cycles, where the number of wait states c ould be quite large (>1 microsecond). however, the lpc47m172 uses a sync of 0110 for al l wait states in an i/o transfer. the sync value is driven within 3 clocks. sync timeout the sync value is driven within 3 clocks. if the host observes 3 consec utive clocks without a valid sync pattern, it will abort the cycle. the lpc47m172 does not assume any particular timeout. when the host is driving sync, it may have to insert a very large number of wait states , depending on pci latencies and retries. sync patterns and maximum number of syncs if the sync pattern is 0101, then the host assume s that the maximum number of syncs is 8. if the sync pattern is 0110, then no maximum num ber of syncs is assumed. the lpc47m172 has protection mechanisms to complete the cycle. this is used for epp da ta transfers and s hould utilize the same timeout protecti on that is in epp.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 36 smsc lpc47m172 datasheet sync error indication the lpc47m172 reports errors vi a the lad[3:0] = 1010 sync encoding. if the host was reading data from the lpc47m172, data wi ll still be transferred in the next two nibbles. this data may be invalid, but it will be transferred by the lpc47m172. if the host was writing data to the lpc47m172, the data had alr eady been transferred. in the case of multiple byte cycles, such as memory and dma cycles, an error sync terminates the cycle. therefore, if the host is transferring 4 bytes from a device, if the device returns the error sync in the first byte, the other three bytes will not be transferred. 6.3.10 i/o and dma start fields i/o and dma cycles use a start field of 0000. reset policy the following rules gove rn the reset policy: when npci_reset goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. this is the same reset active time after clock is stable that is used for the pci bus. when npci_reset goes active (low): ? the host drives the nlframe signal high, trista tes the lad[3:0] signals , and ignores the nldrq signal. ? the lpc47m172 ignores nlframe, tristate the la d[3:0] pins and drive the nldrq signal inactive (high). 6.3.11 lpc transfers wait state requirements i/o transfers the lpc47m172 inserts three wait states for an i/o read and two wa it states for an i/o write cycle. a sync of 0110 is used for all i/o trans fers. the exception to this is for transfers where iochrdy would normally be deasserted in an isa tr ansfer (i.e., epp or ircc transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). dma transfers the lpc47m172 inserts three wait states for a dma re ad and four wait states for a dma write cycle. a sync of 0101 is used for all dma transfers. see the example timing for the lpc cycl es in the ?timing diagrams? section.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 37 smsc lpc47m172 datasheet 6.4 floppy disk controller the floppy disk controller (fdc) provides the inte rface between a host microprocessor and the floppy disk drives. the fdc integrates the functions of the formatter/controller, digita l data separator, write precompensation and data rate selection logic for an ibm xt/at compatible fdc. the true cmos 765b core guarantees 100% ibm pc xt/at compatibility in addition to providing data overflow and underflow protection. the fdc is compatible to the 82077aa using smsc?s proprietary floppy disk controller core. 6.4.1 fdc configuration registers the fdc configuration registers are summarized tabl e 11.2 in the ?configuration? section. the fdc logical device configuration registers (0xf0, 0xf1, 0xf2 and 0xf4) are defined in table 11.9. 6.4.2 fdc internal registers the floppy disk controller contains eight internal regi sters which facilitate the in terfacing between the host microprocessor and the disk drive. table 6.2 show s the addresses required to access these registers. registers other than the ones shown are not supported. the rest of the description assumes that the primary addresses have been selected. table 6.2 - status, data and control registers (shown with base addresses of 3f0 and 370) primary address secondary address r/w register 3f0 3f1 3f2 3f3 3f4 3f4 3f5 3f6 3f7 3f7 370 371 372 373 374 374 375 376 377 377 r r r/w r/w r w r/w r w status register a (sra) status register b (srb) digital output register (dor) tape drive register (tdr) main status register (msr) data rate select register (dsr) data (fifo) reserved digital input register (dir) configuration control register (ccr)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 38 smsc lpc47m172 datasheet 6.4.3 status register a (sra) address 3f0 read only this register is read-only and monito rs the state of the internal interrupt signal and several disk interface pins in ps/2 and model 30 modes. the sra can be ac cessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 ? d7 are held in a high impedance state for a read of address 3f0. ps/2 mode 7 6 5 4 3 2 1 0 int pendin g ndrv2 step ntrk0 hdsel nindx nwp dir reset cond. 0 1 0 n/a 0 n/a n/a 0 bit 0 direction active high status indicating the direction of head move ment. a logic ?1? indicates inward direction; a logic ?0? indicates outward direction. bit 1 nwrite protect active low status of the write protect disk interfac e input. a logic ?0? indicates that the disk is write protected. bit 2 nindex active low status of the index disk interface input. bit 3 head select active high status of the hdsel disk interface input. a logic ?1? selects side 1 and a logic ?0? selects side 0. bit 4 ntrack 0 active low status of the trk0 disk interface input. bit 5 step active high status of the step output disk interface output pin. bit 6 ndrv2 this function is not supported. this bit is always read as ?1?. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output. ps/2 model 30 mode 7 6 5 4 3 2 1 0 int pending drq step f/f trk0 nhdsel index wp ndir reset cond. 0 0 0 n/a 1 n/a n/a 1 bit 0 direction active low status indicating the direction of head move ment. a logic ?0? indicates inward direction; a logic ?1? indicates outward direction.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 39 smsc lpc47m172 datasheet bit 1 write protect active high status of the write pr otect disk interface input. a logic ?1? indicates that the disk is write protected. bit 2 index active high status of t he index disk interface input. bit 3 head select active low status of the hdsel disk interface input. a logic ?0? selects side 1 an d a logic ?1? selects side 0. bit 4 track 0 active high status of the trk0 disk interface input. bit 5 step active high status of the latched step disk interface output pin. this bit is latched with the step output going active, and is cleared with a read from the dir register, or with a hardware or software reset. bit 6 dma request active high status of the dma request pending. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt. 6.4.4 status register b (srb) address 3f1 read only this register is read-only and monitors the state of several disk interface pins in ps/2 and model 30 modes. the srb can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 ? d7 are held in a high impedance state for a read of address 3f1. ps/2 mode 7 6 5 4 3 2 1 0 1 1 drive sel0 wdata toggle rdata toggle wgate mot en1 mot en0 reset cond. 1 1 0 0 0 0 0 0 bit 0 motor enable 0 active high status of the mtr0 disk interface output pin. this bit is low after a hardware reset and unaffected by a software reset. bit 1 motor enable 1 active high status of the mtr1 disk interface output pin. this bit is low after a hardware reset and unaffected by a so ftware reset. bit 2 write gate active high status of t he wgate disk interface output.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 40 smsc lpc47m172 datasheet bit 3 read data toggle every inactive edge of the rdata input causes this bit to change state. bit 4 write data toggle every inactive edge of the wdata input causes this bit to change state. bit 5 drive select 0 reflects the status of the drive se lect 0 bit of the dor (address 3f2 bit 0). this bit is cleared after a hardware reset and it is unaffected by a software reset. bit 6 reserved always read as a logic ?1?. bit 7 reserved always read as a logic ?1? ps/2 model 30 mode 7 6 5 4 3 2 1 0 ndrv2 nds1 nds0 wdata f/f rdata f/f wgate f/f nds3 nds2 reset cond. n/a 1 1 0 0 0 1 1 bit 0 ndrive select 2 the ds2 disk interface is not supported. bit 1 ndrive select 3 the ds3 disk interface is not supported. bit 2 write gate active high status of the latched wgate output signal. this bit is latched by the active going edge of wgate and is cleared by the read of the dir register. bit 3 read data active high status of the latched rda ta output signal. this bit is latched by the inactive going edge of rdata and is cleared by the read of the dir register. bit 4 write data active high status of the latched wdata output signal. this bit is latched by the inactive going edge of wdata and is cleared by the read of the dir register. this bi t is not gated with wgate. bit 5 ndrive select 0 active low status of the ds0 disk interface output. bit 6 ndrive select 1 active low status of the ds1 disk interface output. bit 7 ndrv2 active low status of the drv2 disk interface inpu t. note: this function is not supported.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 41 smsc lpc47m172 datasheet 6.4.5 digital output register (dor) address 3f2 read/write the dor controls the drive select and motor enables of the disk in terface outputs. it also contains the enable for the dma logic and a software reset bit. the contents of the dor ar e unaffected by a software reset. the dor can be written to at any time. 7 6 5 4 3 2 1 0 mot en3 mot en2 mot en1 mot en0 dmaen nreset drive sel1 drive sel0 reset cond. 0 0 0 0 0 0 0 0 bit 0 and 1 drive select these two bits are binary encoded for the drive select s, thereby allowing only one drive to be selected at one time. bit 2 nreset a logic ?0? written to this bit resets the floppy disk cont roller. this reset will remain active until a logic ?1? is written to this bit. this software reset does not affect the dsr and ccr register s, nor does it affect the other bits of the dor register. the minimum reset dur ation required is 100ns, ther efore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. bit 3 dmaen pc/at and model 30 mode: writing this bit to logic ?1? will enable the dma and interrupt functions. this bit being a logic ?0? will disable the dma and interrupt functions. this bit is a logic ?0? after a reset and in these modes. ps/2 mode: in this mode the dma and in terrupt functions are always enabled. during a reset, this bit will be cleared to a logic ?0?. bit 4 motor enable 0 this bit controls the mtr0 disk interface output. a logi c ?1? in this bit will cause the output pin to go active. bit 5 motor enable 1 this bit controls the mtr1 disk interface output. a logi c ?1? in this bit will cause the output pin to go active. drive dor value 0 1ch 1 2dh table 6.3 - internal 2 drive decode - normal digital output register drive select outputs (active low) motor on outputs (active low) bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x 1 0 0 1 0 nbit 5 nbit 4 1 x 0 1 0 1 nbit 5 nbit 4 0 0 x x 1 1 nbit 5 nbit 4
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 42 smsc lpc47m172 datasheet table 6.4 - internal 2 drive decode - drives 0 and 1 swapped digital output register drive select outputs (active low) motor on outputs (active low) bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x 1 0 0 0 1 nbit 4 nbit 5 1 x 0 1 1 0 nbit 4 nbit 5 0 0 x x 1 1 nbit 4 nbit 5 bit 6 motor enable 2 the mtr2 disk interface output is not supported in the lpc47m172. bit 7 motor enable 3 the mtr3 disk interface output is not supported in the lpc47m172. 6.4.6 tape drive register (tdr) address 3f3 read/write the tape drive register (tdr) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive dur ing initialization. any future references to that drive automatically invokes tape support. the tdr tape select bits tdr .[1:0] determine the tape drive number. table 6.5 illustrates the tape select bit encoding. note that drive 0 is the boot device and cannot be assigned tape support. the remaining tape drive register bits tdr.[7:2] are tristated when read. the tdr is unaffected by a software reset. table 6.5 - tape select bits tape sel1 (tdr.1) tape sel0 (tdr.0) drive selected 0 0 1 1 0 1 0 1 none 1 2 3 normal floppy mode normal mode.register 3f3 contains only bits 0 and 1. when this register is read, bits 2 ? 7 are ?0?. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 0 0 0 0 0 0 tape sel1 tape sel0 enhanced floppy mode 2 (os2) register 3f3 for enhanced floppy mode 2 operation. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 reserved reserved drive type id floppy boot drive tape sel1 tape sel0
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 43 smsc lpc47m172 datasheet table 6.6 - drive type id digital output register register 3f3 ? drive type id bit 1 bit 0 bit 5 bit 4 0 0 l0-crf2 ? b1 l0-crf2 ? b0 0 1 l0-crf2 ? b3 l0-crf2 ? b2 1 0 l0-crf2 ? b5 l0-crf2 ? b4 1 1 l0-crf2 ? b7 l0-crf2 ? b6 note: l0-crf2-bx = fdc logical device, configuration register f2, bit x. 6.4.7 data rate select register (dsr) address 3f4 write only this register is write only. it is used to progra m the data rate, amount of write precompensation, power down status, and software reset. the data rate is programmed using the confi guration control register (ccr) not the dsr, for pc/at and ps/2 model 30. 7 6 5 4 3 2 1 0 s/w reset power down 0 pre- comp2 pre- comp1 pre- comp0 drate sel1 drate sel0 reset cond. 0 0 0 0 0 0 1 0 this register is write only. it is used to progra m the data rate, amount of write precompensation, power down status, and software reset. the data rate is programmed using the confi guration control register (ccr) not the dsr, for pc/at and ps/2 model 30. other applications can set the data ra te in the dsr. the data rate of the floppy controller is the most recent write of either the dsr or ccr. the dsr is unaffected by a software reset. a hardware reset will set the dsr to 02h, which corresponds to th e default precompensation setting and 250 kbps. bit 0 and 1 data rate select these bits control the data rate of the floppy controller. see table 6.8 for the settings corresponding to the individual data rates. the data rate select bits ar e unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 through 4 precompensation select these three bits select the value of write precompensatio n that will be applied to the wdata output signal. table 6.7 shows the precompensation values fo r the combination of these bits settings. track 0 is the default starting track number to start precompensation. this st arting track number can be changed by the configure command.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 44 smsc lpc47m172 datasheet table 6.7 - precompensation delays precomp 432 precompensation delay (nsec) <2mbps 2mbps 111 001 010 011 100 101 110 000 0.00 41.67 83.34 125.00 166.67 208.33 250.00 default 0 20.8 41.7 62.5 83.3 104.2 125 default default: see table 6.10 bit 5 undefined should be written as a logic ?0?. bit 6 low power a logic ?1? written to this bit will put the floppy controller into manual low power mode. the floppy controller clock and data separator ci rcuits will be turned off. the contro ller will come out of manual low power mode after a software reset or access to the data register or main status register. bit 7 software reset this active high bit has the same function as the dor reset (dor bit 2) except that this bit is self clearing. separator circuits will be turned off. the c ontroller will come out of manual low power. note: the dsr is shadowed in the floppy data rate select s hadow register, located at the offset 0x19 in the power control/runtime register block. table 6.8 - data rates drive rate data rate data rate drate(1) drt1 drt0 sel1 sel0 mfm fm densel 1 0 0 0 1 1 1meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0 0 1 1 1 1meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0 1 0 1 1 1meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2meg --- 0 0 1 1 0 1 0 250 125 0 1 0 drive rate table (recommended) 00 = 360k, 1.2m, 720k, 1.44m and 2.88m vertical format 01 = 3-mode drive 10 = 2 meg tape note 1: the drate and densel values are mapped onto the drvden pins.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 45 smsc lpc47m172 datasheet table 6.9 - drvden mapping dt1 dt0 drvden1 (1) drvden0 (1) drive type 0 0 drate0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? fdds 2/1.6/1 mb 3.5? (3-mode) 1 0 drate0 drate1 0 1 drate0 ndensel ps/2 1 1 drate1 drate0 table 6.10 - default precompensation delays data rate precompensation delays 2 mbps 1 mbps 500 kbps 300 kbps 250 kbps 20.8 ns 41.67 ns 125 ns 125 ns 125 ns 6.4.8 main status register address 3f4 read only the main status register is a read-o nly register and indicates the status of the disk controller. the main status register can be read at any time. the msr in dicates when the disk controller is ready to receive data via the data register. it should be read before each byte transferring to or from the data register except in dma mode. no delay is requir ed when reading the msr after a data transfer. 7 6 5 4 3 2 1 0 rqm dio non dma cmd busy reserved reserved drv1 busy drv0 busy bit 0 ? 1 drv x busy these bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. bit 4 command busy this bit is set to a 1 when a command is in progress. this bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. if there is no result phase (seek, recalibrate commands), this bit is return ed to a 0 after the last command byte. bit 5 non-dma reserved, read ?0?. this part does not support non-dma mode. bit 6 dio indicates the direction of a data trans fer once a rqm is set. a 1 indicates a read and a 0 indicates a write is required. bit 7 rqm indicates that the host can transfer data if set to a 1. no access is permitted if set to a 0.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 46 smsc lpc47m172 datasheet 6.4.9 data register (fifo) address 3f5 read/write all command parameter information, disk data and re sult status are transferred between the host processor and the floppy disk controll er through the data register. data transfers are governed by the rqm and dio bits in the main status register. the data register defaults to fifo disabled mode after any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command (enable full fifo operation with threshold control). the advantage of the fifo is that it allows the system a larger dma latency without causing a disk e rror. table 6.11 gives several examples of the delays with a fifo. the data is based upon the following formula: threshold # x 1 data rate x 8 - 1.5 us = delay at the start of a command, the fifo action is al ways disabled and command parameters must be sent based upon the rqm and dio bit settings. as the command execution phase is entered, the fifo is cleared of any data to ensure that invalid data is not transferred. an overrun or underrun will terminate the current command and the transfer of data. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered. table 6.11 - fifo service delay fifo threshold examples maximum delay to servicing at 2 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 4 us - 1.5 us = 2.5 us 2 x 4 us - 1.5 us = 6.5 us 8 x 4 us - 1.5 us = 30.5 us 15 x 4 us - 1.5 us = 58.5 us fifo threshold examples maximum delay to servicing at 1 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 8 us - 1.5 us = 6.5 us 2 x 8 us - 1.5 us = 14.5 us 8 x 8 us - 1.5 us = 62.5 us 15 x 8 us - 1.5 us = 118.5 us fifo threshold examples maximum delay to servicing at 500 kbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 16 us - 1.5 us = 14.5 us 2 x 16 us - 1.5 us = 30.5 us 8 x 16 us - 1.5 us = 126.5 us 15 x 16 us - 1.5 us = 238.5 us
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 47 smsc lpc47m172 datasheet 6.4.10 digital input register (dir) address 3f7 read only this register is read-only in all modes. pc-at mode 7 6 5 4 3 2 1 0 dsk chg 0 0 0 0 0 0 0 reset cond. n/a n/a n/a n/a n/a n/a n/a n/a bit 0 ? 6 undefined the data bus outputs d0 ? 6 are read as ?0?. bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see power control/runtime register block runtime register at offset 0x18). ps/2 mode 7 6 5 4 3 2 1 0 dsk chg 1 1 1 1 drate sel1 drate sel0 nhigh dens reset cond. n/a n/a n/a n/a n/a n/a n/a 1 bit 0 nhigh dens this bit is low whenever the 500 kbps or 1 mbps data rates are selected, and high when 250 kbps and 300 kbps are selected. bits 1 ? 2 data rate select these bits control the data rate of the floppy controller. see table 6.8 for the settings corresponding to the individual data rates. the data rate select bits ar e unaffected by a software reset, and are set to 250 kbps after a hardware reset. bits 3 ? 6 undefined always read as a logic ?1? bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see power control/runtime register block runtime register at offset 0x18). model 30 mode 7 6 5 4 3 2 1 0 dsk chg 0 0 0 dmaen noprec drate sel1 drate sel0 reset cond. n/a 0 0 0 0 0 1 0
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 48 smsc lpc47m172 datasheet bits 0 ? 1 data rate select these bits control the data rate of the floppy controller. see table 6.8 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 noprec this bit reflects the value of no prec bit set in the ccr register. bit 3 dmaen this bit reflects the value of dmaen bit set in the dor register bit 3. bits 4 ? 6 undefined always read as a logic ?0? bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see power control/runtime register block runtime register at offset 0x18). 6.4.11 configuration c ontrol register (ccr) address 3f7 write only pc/at and ps/2 modes 7 6 5 4 3 2 1 0 0 0 0 0 0 0 drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy c ontroller. see table 6.8 for the appropriate values. bit 2 ? 7 reserved should be set to a logical ?0? ps/2 model 30 mode 7 6 5 4 3 2 1 0 0 0 0 0 0 noprec drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy c ontroller. see table 6.8 for the appropriate values. bit 2 no precompensation this bit can be set by software, but it has no functi onality. it can be read by bit 2 of the dsr when in model 30 register mode. unaffected by software reset.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 49 smsc lpc47m172 datasheet bit 3 ? 7 reserved should be set to a logical ?0? table 6.9 shows the state of the de nsel pin. the densel pin is set high after a hardware reset and is unaffected by the dor and the dsr resets. 6.4.12 status register encoding during the result phase of certain commands, the data register contains data bytes that give the status of the command just executed. table 6.12 - status register 0 bit no. symbol name description 7,6 ic interrupt code 00 - normal termination of command. the specified command was properly executed and completed without error. 01 - abnormal termination of command. command execution was started, but was not successfully completed. 10 - invalid command. the requested command could not be executed. 11 - abnormal termination caused by polling. 5 se seek end the fdc completed a seek, relative seek or recalibrate command (used during a sense interrupt command). 4 ec equipment check the trk0 pin failed to become a "1" after: 1. step pulses in the recalibrate command. 2. the relative seek command caused the fdc to step outward beyond track 0. 3 unused. this bit is always "0". 2 h head address the current head address. 1,0 ds1,0 drive select t he current selected drive. table 6.13 - status register 1 bit no. symbol name description 7 en end of cylinder the fdc tried to access a sector beyond the final sector of the track (255d). will be set if tc is not issued after read or write data command. 6 unused. this bit is always "0". 5 de data error the fdc detected a crc error in either the id field or the data field of a sector. 4 or overrun/ underrun becomes set if the fdc does not receive cpu or dma service within the required time interval, resulting in data overrun or underrun. 3 unused. this bit is always "0".
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 50 smsc lpc47m172 datasheet bit no. symbol name description 2 nd no data any one of the following: 1. read data, read deleted data command - the fdc did not find the specified sector. 2. read id command - the fdc cannot read the id field without an error. 3. read a track command - the fdc cannot find the proper sector sequence. 1 nw not writeable wp pin became a "1" while the fdc is executing a write data, write deleted data, or format a track command. 0 ma missing address mark any one of the following: 1. the fdc did not detect an id address mark at the specified track after encountering the index pulse from the nindex pin twice. 2. the fdc cannot detect a data address mark or a deleted data address mark on the specified track. table 6.14 - status register 2 bit no. symbol name description 7 unused. this bit is always "0". 6 cm control mark any one of the following: read data command - the fdc encountered a deleted data address mark. read deleted data command - the fdc encountered a data address mark. 5 dd data error in data field the fdc detected a crc erro r in the data field. 4 wc wrong cylinder the track address from the sector id field is different from the track address maintained inside the fdc. 3 unused. this bit is always "0". 2 unused. this bit is always "0". 1 bc bad cylinder the track address from the sector id field is different from the track address maintained inside the fdc and is equal to ff hex, which indicates a bad track with a hard error according to the ibm soft-sectored format. 0 md missing data address mark the fdc cannot detect a data address mark or a deleted data address mark. table 6.15 - status register 3 bit no. symbol name description 7 unused. this bit is always "0". 6 wp write protected indicates the status of the wrtprt pin. 5 unused. this bit is always "1". 4 t0 track 0 indicates the status of the trk0 pin. 3 unused. this bit is always "1". 2 hd head address indicates the status of the hdsel pin. 1,0 ds1,0 drive select indicates the status of the ds1, ds0 pins.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 51 smsc lpc47m172 datasheet reset there are three sources of system reset on the fdc: the npci_reset pin, a rese t generated via a bit in the dor, and a reset generated via a bi t in the dsr. at power on, a power on reset initializes the fdc. all resets take the fdc out of the power down state. all operations are terminated upon a npci_reset, and the fdc enters an idle state. a reset while a disk write is in progress will corrupt the data and crc. on exiting the reset state, various internal re gisters are cleared, including the configure command information, and the fdc waits for a new command. drive polling will start unless disabled by a new configure command. npci_reset pin (hardware reset) the npci_reset pin is a global reset and clears all registers except those programmed by the specify command. the dor reset bit is enabled and must be cl eared by the host to exit the reset state. dor reset vs. dsr reset (software reset) these two resets are functionally the same. both will reset the fdc core, which affects drive status information and the fifo circuits. the dsr reset clears itself automatically whil e the dor reset requires the host to manually clear it. dor reset has precedence over the dsr reset. the dor reset is set automatically upon a pin reset. the user must manually clear this reset bit in the dor to exit the reset state. 6.5 modes of operation the fdc has three modes of operation, pc/at mode, ps/2 mode and mode l 30 mode. these are determined by the state of the interface mode bits in fdc logical device -crf0[3,2]. 6.5.1 pc/at mode the pc/at register set is enabled, the dma enable bi t of the dor becomes valid (controls the interrupt and dma functions), and densel is an active high signal. 6.5.2 ps/2 mode this mode supports the ps/2 models 50/60/80 configuration and regist er set. the dma bit of the dor becomes a ?don?t care?. the dma and interrupt function s are always enabled, and densel is active low. 6.5.3 model 30 mode this mode supports ps/2 model 30 configuration and register set. the dma enable bit of the dor becomes valid (controls the interrupt and dma functions), and densel is active low. 6.6 dma transfers dma transfers are enabled with the specify command and are initiated by the fdc by activating a dma request cycle. dma read, write and verify cycles are supported. the fdc supports two dma transfer modes: single transfer and burst transfer. burst mode is enabled via fdc logical device -crf0-bit[1].
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 52 smsc lpc47m172 datasheet 6.7 controller phases for simplicity, command handling in the fdc can be di vided into three phases: command, execution, and result. each phase is described in the following sections. 6.7.1 command phase after a reset, the fdc enters the command phase and is ready to accept a command from the host. for each of the commands, a defined set of command code bytes and parameter bytes has to be written to the fdc before the command phase is complete. (please refer to section 6.10 command set/descriptions). these bytes of data must be transferred in the order prescribed. before writing to the fdc, the host must examine t he rqm and dio bits of the main status register. rqm and dio must be equal to ?1? and ?0? respectively before command bytes may be written. rqm is set false by the fdc after each write cycle until the received byte is processed. the fdc asserts rqm again to request each parameter byte of the command unless an illegal command condition is detected. after the last parameter byte is received, rqm re mains ?0? and the fdc automat ically enters the next phase as defined by the command definition. the fifo is disabled during the command phase to provide for the proper handling of the ?invalid command? condition. 6.7.2 execution phase all data transfers to or from the fdc occur during the execution phase, which can proceed in dma mode as indicated in the specify command. after a reset, the fifo is disabled. each data byte is transferred by a read/write or dma cycle depending on the dma mode. the configure command can enab le the fifo and set the fifo threshold value. the following paragraphs detail the operation of the fifo flow control. in these descriptions, is defined as the number of bytes available to t he fdc when service is requested from the host and ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host reads (writes) from (to) the fifo until empty (full), then the transfer request goes inactive. the host must be very responsive to the service request. this is the desired case for use with a ?fast? system. a high value of threshold (i.e. 12) is used with a ?sluggish? system by affording a long latency period after a service request, but results in more frequent service requests. non-dma mode - transfers from the fifo to the host this part does not support non-dma mode. non-dma mode - transfers from the host to the fifo this part does not support non-dma mode.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 53 smsc lpc47m172 datasheet dma mode - transfers from the fifo to the host the fdc generates a dma request cycle when the fifo contai ns (16 - ) bytes, or the last byte of a full sector transfer has been placed in the fifo. the dma controller must respond to the request by reading data from the fifo. the fdc will deactivate the dma request when the fifo becomes empty by generating the proper sync for the data transfer. dma mode - transfers from the host to the fifo. the fdc generates a dma request cycle when ente ring the execution phase of the data transfer commands. the dma controller must respond by plac ing data in the fifo. the dma request remains active until the fifo becomes full. the dma request cycle is reasserted when the fifo has bytes remaining in the fifo. the fdc will terminate the dma cycle after a tc, indicating that no more data is required. 6.8 data transfer termination the fdc supports terminal count explicitly through the tc pin and implicitly through the underrun/overrun and end-of-track (eot) functions. for full sector trans fers, the eot parameter c an define the last sector to be transferred in a single or multi-sector transfer. if the last sector to be transferred is a partial sector , the host can stop transferri ng the data in mid-sector, and the fdc will continue to complete the sector as if a tc cycle was received. the only difference between these implicit functions and tc cycle is that they return ?abnormal termination? result status. such status indications can be ignored if they were expected. note that when the host is sending data to the fifo of the fdc, the internal sector count will be complete when the fdc reads the last byte fr om its side of the fifo. there may be a delay in the removal of the transfer request signal of up to the time taken for the fdc to read the last 16 bytes from the fifo. the host must tolerate this delay. 6.9 result phase the generation of the interrupt determines the beginning of the result phase. for each of the commands, a defined set of result bytes has to be read from the fdc before the result phase is complete. these bytes of data must be read out for another command to start. rqm and dio must both equal ?1? bef ore the result bytes may be read. after all the result bytes have been read, the rqm and dio bits switch to ?1? and ?0? respectively, and the cb bit is cleared, indicating that the fdc is ready to accept the next command. 6.10 command set/descriptions commands can be written whenever the fdc is in t he command phase. each command has a unique set of needed parameters and status result s. the fdc checks to see that the first byte is a valid command and, if valid, proceeds with the command. if it is invalid, an interrupt is issued. the user sends a sense interrupt status command which returns an invalid command error. refer to table 6.16 for explanations of the various symbols used. table 6.17 lists the required parameters and the results associated with each command that the fdc is capable of performing.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 54 smsc lpc47m172 datasheet table 6.16 - description of command symbols symbol name description c cylinder address the currently selected address; 0 to 255. d data pattern the pattern to be written in each sector data field during formatting. d0, d1 drive select 0-1 designates which drives are perpendicular drives on the perpendicular mode command. a ?1? indicates a perpendicular drive. dir direction control if this bit is 0, then the head will step out from the spindle during a relative seek. if set to a 1, the head will step in toward the spindle. ds0, ds1 disk drive select ds1 ds0 drive 0 0 drive 0 0 1 drive 1 dtl special sector size by setting n to zero (00), dtl ma y be used to control the number of bytes transferred in disk read/write commands. the sector size (n = 0) is set to 128. if the actual sector (on the diskette) is larger than dtl, the remainder of the ac tual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. the crc check code is calculated with the actual sector. when n is not zero, dtl has no meaning and should be set to ff hex. ec enable count when this bit is ?1? the ?dtl? parameter of the verify command becomes sc (number of sectors per track). efifo enable fifo this active low bit when a 0, enables the fifo. a ?1? disables the fifo (default). eis enable implied seek when set, a seek operation will be performed before executing any read or write command that requires the c parameter in the command phase. a ?0? disables the implied seek. eot end of track the final sector number of the current track. gap alters gap 2 length when using perpendicular mode. gpl gap length the gap 3 size. (gap 3 is the space between sectors excluding the vco synchronization field). h/hds head address selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector id field. hlt head load time the time interval that fdc wait s after loading the head and before initializing a read or write operati on. refer to the specify command for actual delays. hut head unload time the time interval from the end of the execution phase (of a read or write command) until the head is unloaded. refer to the specify command for actual delays. lock lock defines whether efifo, fifothr, and pretrk parameters of the configure command can be reset to their default values by a ?software reset?. (a reset caused by writing to the appropriate bits of either the dsr or dor) mfm mfm/fm mode selector a one selects the double density (mfm) mode. a zero selects single density (fm) mode. mt multi-track selector when set, this flag selects the multi- track operating mode. in this mode, the fdc treats a complete cylinder under head 0 and 1 as a single track. the fdc operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. with this flag set, a multitrack read or write operation will automatically continue to the firs t sector under head 1 when the fdc finishes operating on the last sector under head 0.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 55 smsc lpc47m172 datasheet symbol name description n sector size code this specifies the number of bytes in a sector. if this parameter is "00", then the sector size is 128 bytes. the number of bytes transferred is determined by the dtl parameter. otherwise the sector size is (2 raised to the "n'th" power) times 128. all values up to "07" hex are allowable. "07"h would equal a sector size of 16k. it is the user's responsibility to not select combinations that are not possible with the drive. n sector size 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes ? ? 07 16k bytes ncn new cylinder number the desired cylinder number. nd non-dma mode flag write ?0?. this part does not support non-dma mode. ow overwrite the bits d0-d3 of the perpendicular mode command can only be modified if ow is set to 1. ow id defined in the lock command. pcn present cylinder number the current position of the head at the completion of sense interrupt status command. poll polling disable when set, the internal polling routine is disabled. when clear, polling is enabled. pretrk precompensation start track number programmable from track 00 to ffh. r sector address the sector number to be read or written. in multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. rcn relative cylinder number relative cylinder offset from present cylinder as used by the relative seek command. sc number of sectors per track the number of sectors per track to be initialized by the format command. the number of sectors per track to be verified during a verify command when ec is set. sk skip flag when set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of read data. if read deleted is executed, only sectors with a deleted address mark will be accessed. when set to ?0?, the sector is read or written the same as the read and write commands. srt step rate interval the time interval between step pulses issued by the fdc. programmable from 0.5 to 8 millisecon ds in increments of 0.5 ms at the 1 mbit data rate. refer to the specify command for actual delays. st0 st1 st2 st3 status 0 status 1 status 2 status 3 registers within the fdc which store status information after a command has been executed. this status information is available to the host during the result phase after command execution. wgate write gate alters timing of we to allow for pre-erase loads in perpendicular drives.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 56 smsc lpc47m172 datasheet 6.10.1 instruction set table 6.17 - instruction set read data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after com- mand execution. r st1 r st2 r c sector id information after command execution. r h r r r n read deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after com- mand execution. r st1 r st2 r c sector id information after command execution. r h r r r n
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 57 smsc lpc47m172 datasheet write data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after com- mand execution. r st1 r st2 r c sector id information after command execution. r h r r r n write deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after command execution. r st1 r st2 r c sector id information after command execution. r h r r r n
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 58 smsc lpc47m172 datasheet read a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. fdc reads all of cylinders? contents from index hole to eot. result r st0 status information after command execution. r st1 r st2 r c sector id information after command execution. r h r r r n verify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl/sc execution no data transfer takes place. result r st0 status information after command execution. r st1 r st2 r c sector id information after command execution. r h r r r n
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 59 smsc lpc47m172 datasheet version data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller format a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w n bytes/sector w sc sectors/cylinder w gpl gap 3 w d filler byte execution for each sector repeat: w c input sector parameters w h w r w n fdc formats an entire cylinder result r st0 status information after command execution r st1 r st2 r undefined r undefined r undefined r undefined recalibrate data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt. sense interrupt status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command codes result r st0 status information at the end of each seek operation. r pcn specify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w srt hut w hlt nd
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 60 smsc lpc47m172 datasheet sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 result r st3 status information about fdd seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w ncn execution head positioned over proper cylinder on diskette. configure data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure information w 0 0 0 0 0 0 0 0 w 0 eis efifo poll fifothr execution w pretrk relative seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 w 0 0 0 0 0 hds ds1 ds0 w rcn dumpreg data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 *note: registers placed in fifo execution result r pcn-drive 0 r pcn-drive 1 r pcn-drive 2 r pcn-drive 3 r srt hut r hlt nd r sc/eot r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll fifothr r pretrk
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 61 smsc lpc47m172 datasheet read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 commands w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r st0 status information after command execution. disk status after the command has completed r st1 r st2 r c r h r r r n perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command codes ow 0 d3 d2 d1 d0 gap wgate invalid codes data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w invalid codes invalid command codes (noop ? fdc goes into standby state) result r st0 st0 = 80h lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command codes result r 0 0 0 lock 0 0 0 0 sc is returned if the last command that was issued was the format command. eot is returned if the last command was a read or write. note: these bits are used internally only. they are not re flected in the drive select pins. it is the user?s responsibility to maintain correspondence between these bits and the drive select pins (dor).
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 62 smsc lpc47m172 datasheet 6.11 data transfer commands all of the read data, write data and verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. an implied seek will be executed if the feature was enabled by the configure command. this seek is completely transparent to the user. the drive busy bit for the drive will go active in the main status register during the seek portion of the command. if th e seek portion fails, it is reflected in the results status normally returned for a read/write data command. status register 0 (st0 ) would contain the error code and c would contain the cyli nder on which the seek failed. 6.11.1 read data a set of nine (9) bytes is required to place the fdc in the read data mode. after the read data command has been issued, the fdc loads the head (if it is in the unloaded state) , waits the specified head settling time (defined in the specify command), and begi ns reading id address marks and id fields. when the sector address read off the diskette matches with the sector address specified in the command, the fdc reads the sector?s data field a nd transfers the data to the fifo. after completion of the read operation from the curre nt sector, the sector addre ss is incremented by one and the data from the next logical sector is read and out put via the fifo. this continuous read function is called ?multi-sector read operation?. upon receip t of the tc cycle, or an implied tc (fifo overrun/underrun), the fdc stops se nding data but will continue to read data from the current sector, check the crc bytes, and at the end of t he sector, terminate the read data command. n determines the number of bytes per sector (see table 6. 18 below). if n is set to zero, the sector size is set to 128. the dtl value determines the number of by tes to be transferred. if dtl is less than 128, the fdc transfers the specified number of bytes to the host. for reads, it continues to read the entire 128- byte sector and checks for crc errors. for writes, it completes the 128-byte sector by filling in zeros. if n is not set to 00 hex, dtl should be set to ff hex an d has no impact on the number of bytes transferred. table 6.18 - sector sizes n sector size 00 01 02 03 .. 07 128 bytes 256 bytes 512 bytes 1024 bytes ? 16 kbytes the amount of data which can be handled with a single command to the fdc depends upon mt (multi- track) and n (number of bytes/sector). the multi-track function (mt) allows the fdc to read data from both sides of the diskette. for a particular cylinder, data will be transferred starti ng at sector 1, side 0 and comple ting the last sector of the same track at side 1. if the host terminates a read or write operation in t he fdc, the id information in the result phase is dependent upon the state of the mt bit and eot byte. refer to table 6.19.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 63 smsc lpc47m172 datasheet at the completion of the read data command, the head is not unloaded until after the head unload time interval (specified in the specify command) has elaps ed. if the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. if the fdc detects a pulse on the nindex pin twice wi thout finding the specified sector (meaning that the diskette?s index hole passes through index detect logic in the drive twice), the fdc sets the ic code in status register 0 to ?01? indicating abnormal termi nation, sets the nd bit in status register 1 to ?1? indicating a sector not found, and terminates the read data command. after reading the id and data fields in each sector , the fdc checks the crc bytes. if a crc error occurs in the id or data field, the fdc sets the ic code in status register 0 to ?01? indicating abnormal termination, sets the de bit flag in st atus register 1 to ?1?, sets the dd bit in status register 2 to ?1? if crc is incorrect in the id field, and terminates the read data command. table 6.20 describes the effect of the sk bit on the read data command execution and results. except where noted in table 6.20, the c or r value of the sector address is aut omatically incremented (see table 6.22). table 6.19 - effects of mt and n bits mt n maximum transfer capacity final sector read from disk 0 1 0 1 0 1 1 1 2 2 3 3 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1 table 6.20 - skip bit vs read data command results sk bit value data address mark type encountered sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes yes no no yes no yes normal termination. address not incremented. next sector not searched for. normal termination. normal termination. sector not read (?skipped?). 6.12 read deleted data this command is the same as the read data command, only it operates on sector s that contain a deleted data address mark at the beginning of a data field. table 6.21 describes the effect of the sk bit on the read deleted data command execution and results. except where noted in table 6.21, the c or r value of the sector address is automatically incremented (see table 6.22).
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 64 smsc lpc47m172 datasheet table 6.21 - skip bit vs. read deleted data command results sk bit value data address mark type encountered sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes no yes yes no yes no address not incremented. next sector not searched for. normal termination. normal termination. sector not read (?skipped?). normal termination. 6.13 read a track this command is similar to the read data command ex cept that the entire data fi eld is read continuously from each of the sectors of a tra ck. immediately after encountering a pulse on the nindex pin, the fdc starts to read all data fields on the track as contin uous blocks of data without regard to logical sector numbers. if the fdc finds an error in the id or data crc check bytes, it continues to read data from the track and sets the appropriate error bits at t he end of the command. the fdc compares the id information read from each sector with the specified value in the command and sets the nd flag of status register 1 to a ?1? if there no comparison. multi- track or skip operations are not allowed with this command. the mt and sk bits (bits d7 and d5 of the first command byte respectively) should always be set to ?0?. this command terminates when the eot specified number of sectors has not been read. if the fdc does not find an id address mark on the diskette after t he second occurrence of a pulse on the nindex pin, then it sets the ic code in status register 0 to ? 01? (abnormal termination), sets the ma bit in status register 1 to ?1?, and terminates the command. table 6.22 - result phase table mt head final sector transferred to id information at result phase host c h r n 0 0 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 0 less than eot nc nc r + 1 nc equal to eot nc lsb 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 lsb 01 nc nc: no change, the same value as the one at the beginning of command execution. lsb: least significant bit, the lsb of h is complemented.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 65 smsc lpc47m172 datasheet 6.14 write data after the write data command has been issued, the f dc loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defin ed in the specify command), and begins reading id fields. when the sector address read from the disk ette matches the sector address specified in the command, the fdc reads the data from the host via t he fifo and writes it to the sector?s data field. after writing data into the current sector, the fdc comp utes the crc value and writes it into the crc field at the end of the sector transfer. the sector number stored in ?r? is incremented by one, and the fdc continues writing to the next data field. the fdc co ntinues this ?multi-sector write operation?. upon receipt of a terminal count signal or if a fifo over/un der run occurs while a data field is being written, then the remainder of the data field is f illed with zeros. the fdc reads the id field of each sector and checks the crc bytes. if it detects a crc error in one of the id fields, it sets the ic code in status register 0 to ?01? (abnormal termination), sets the de bit of stat us register 1 to ?1?, and terminates the write data command. the write data command operates in much the same manner as the read data command. the following items are the same. please refer to the read data command for details: ? transfer capacity ? en (end of cylinder) bit ? nd (no data) bit ? head load, unload time interval ? id information when the host terminates the command definition of dtl when n = 0 and when n does not = 0 6.15 write deleted data this command is almost the same as the write data command except that a deleted data address mark is written at the beginning of the data field instead of the normal data address mark. this command is typically used to mark a bad sector containing an error on the floppy disk. 6.16 verify the verify command is used to verify the data stored on a disk. this command acts exactly like a read data command except that no data is transferred to the host. data is read from the disk and crc is computed and checked against the previously-stored value. because data is not transferred to the host, the tc cycle cannot be used to terminate this command. by setting the ec bit to ?1?, an implicit tc will be issued to the fdc. this implicit tc will occur when the sc value has decremented to 0 (an sc value of 0 will verify 256 sectors). this command can also be terminated by setting the ec bit to ?0? and the eot value equal to the final sector to be checked. if ec is set to ?0?, dtl/sc should be programmed to 0ffh. refer to table 6.22 and table 6.23 for information concerning the values of mt and ec versus sc and eot value. definitions: # sectors per side = number of formatt ed sectors per each side of the disk. # sectors remaining = number of formatted sectors left which can be read, including side 1 of the disk if mt is set to ?1?.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 66 smsc lpc47m172 datasheet table 6.23 - verify command result phase table mt ec sc/eot value termination result 0 0 sc = dtl eot <= # sectors per side success termination result phase valid 0 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 0 1 sc <= # sectors remaining and eot <= # sectors per side successful termination result phase valid 0 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid 1 0 sc = dtl eot <= # sectors per side successful termination result phase valid 1 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 1 1 sc <= # sectors remaining and eot <= # sectors per side successful termination result phase valid 1 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid note: if mt is set to ?1? and the sc value is greater t han the number of remaining formatted sectors on side 0, verifying will continue on side 1 of the disk. 6.17 format a track the format command allows an entire track to be formatted. after a pulse from the nindex pin is detected, the fdc starts writing data on the disk in cluding gaps, address marks, id fields, and data fields per the ibm system 34 or 3740 format (mfm or fm respec tively). the particular values that will be written to the gap and data field are controlled by the va lues programmed into n, sc, gpl, and d which are specified by the host during the command phase. the data field of the sector is filled with the data byte specified by d. the id field for each sector is suppli ed by the host; that is, four data bytes per sector are needed by the fdc for c, h, r, and n (cylinder, head, sector number and sector size respectively). after formatting each sector, the host must send new val ues for c, h, r and n to the fdc for the next sector on the track. the r value (sector number) is the only value that must be changed by the host after each sector is formatted. this allows the disk to be formatted with nonsequential sector addresses (interleaving). this incrementing and formatting conti nues for the whole track until the fdc encounters a pulse on the nindex pin again and it terminates the command. table 6.24 contains typical values for gap fields t hat are dependent upon the size of the sector and the number of sectors on each track. actual va lues can vary due to drive electronics.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 67 smsc lpc47m172 datasheet format fields system 34 (double density) format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l h d s e c n o c r c gap2 22x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8 system 3740 (single density) format gap4a 40x ff sync 6x 00 iam gap1 26x ff sync 6x 00 idam c y l h d s e c n o c r c gap2 11x ff sync 6x 00 data am data c r c gap3 gap 4b fc fe fb or f8 perpendicular format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l h d s e c n o c r c gap2 41x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8 table 6.24 - typical values for formatting format sector size n sc gpl1 gpl2 5.25? drives fm 128 128 512 1024 2048 4096 ... 00 00 02 03 04 05 ... 12 10 08 04 02 01 07 10 18 46 c8 c8 09 19 30 87 ff ff mfm 256 256 512* 1024 2048 4096 ... 01 01 02 03 04 05 ... 12 10 09 04 02 01 0a 20 2a 80 c8 c8 0c 32 50 f0 ff ff 3.5? drives fm 128 256 512 0 1 2 0f 09 05 07 0f 1b 1b 2a 3a mfm 256 512** 1024 1 2 3 0f 09 05 0e 1b 35 36 54 74 gpl1 = suggested gpl values in read and write commands to avoid splice point between data field and id field of contiguous sections. gpl2 = suggested gpl value in format a track command. *pc/at values (typical) **ps/2 values (typical). applies with 1.0 mb and 2.0 mb drives. note: all values except sector size are in hex.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 68 smsc lpc47m172 datasheet 6.18 control commands control commands differ from the other commands in that no data transfer takes place. three commands generate an interrupt when complete: read id, recali brate, and seek. the other control commands do not generate an interrupt. 6.18.1 read id the read id command is used to find the present position of the recording heads. the fdc stores the values from the first id field it is able to read into its registers. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the nindex pin, it then sets the ic code in status register 0 to ?01? (abnormal termination), sets the ma bit in status register 1 to ?1?, and terminates the command. the following commands will generate an interrupt upon co mpletion. they do not return any result bytes. it is highly recommended that control commands be fo llowed by the sense interrupt status command. otherwise, valuable interrupt status information will be lost. 6.18.2 recalibrate this command causes the read/write head within the f dc to retract to the track 0 position. the fdc clears the contents of the pcn counter and checks the status of the ntrk0 pin from t he fdd. as long as the ntrk0 pin is low, the dir signal remains 0 and step pulses are issued. when the ntrk0 pin goes high, the se bit in status register 0 is set to ?1 ? and the command is terminated. if the ntrk0 pin is still low after 255 step pulses have been issued, the fdc sets the se and the ec bits of status register 0 to ?1? and terminates the command. disks capable of handling more than 256 tracks per side may require more than one recalibrate command to return the head back to physical track 0. the recalibrate command does not have a result phas e. the sense interrupt status command must be issued after the recalibrate command to effectively terminate it and to provide verification of the head position (pcn). during the command phase of the recali brate operation, the fdc is in the busy state, but during the execution phase it is in a non-busy state. at this time , another recalibrate command may be issued, and in this manner parallel recalibrate operations may be done on up to four drives at once. upon power up, the software must issue a recalibrate command to properly initialize all drives and the controller. 6.18.3 seek the read/write head within the drive is moved from tr ack to track under the control of the seek command. the fdc compares the pcn, which is the current head position, with the ncn and performs the following operation if there is a difference: pcn < ncn: direction signal to drive set to ?1? (step in) and issues step pulses. pcn > ncn: direction signal to drive set to ?0? (step out) and issues step pulses. the rate at which step pulses are issued is cont rolled by srt (stepping rate time) in the specify command. after each step pulse is issued, ncn is compared against pcn, and when ncn = pcn the se bit in status register 0 is set to ?1? and the command is terminated. during the command phase of the seek or recalibrate operation, the fdc is in the bu sy state, but during the exec ution phase it is in the non-busy state. at this time, another seek or reca librate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 69 smsc lpc47m172 datasheet note that if implied seek is not enabled, the read and write commands should be preceded by: 1. seek command - step to the proper track 2. sense interrupt status command - terminate the seek command 3. read id - verify head is on proper track 4. issue read/w rite command. the seek command does not have a result phase. ther efore, it is highly re commended that the sense interrupt status command is issued after the seek co mmand to terminate it and to provide verification of the head position (pcn). the h bit (head address) in st0 will always return to a ?0?. when exiting powerdown mode, the fdc clears the pcn value and the status information to ze ro. prior to issuing the powerdown command, it is highly recommended that the user service all pending interrupts through the sense interrupt status command. 6.19 sense interrupt status an interrupt signal is generated by the fdc for one of the following reasons: 1. upon entering the result phase of: a. read data command b. read a track command c. read id command d. read deleted data command e. write data command f. format a track command g. write deleted data command h. verify command 2. end of seek, relative seek, or recalibrate command the sense interrupt status command resets the interru pt signal and, via the ic code and se bit of status register 0, identifies the cause of the interrupt. table 6.25 - interrupt identification se ic interrupt due to 0 1 1 11 00 01 polling normal termination of seek or recalibrate command abnormal termination of seek or recalibrate command the seek, relative seek, and recalibrate commands hav e no result phase. the sense interrupt status command must be issued immediately after these commands to terminate them and to provide verification of the head position (pcn). the h (head address) bit in st0 will always return a ?0?. if a sense interrupt status is not issued, the drive wi ll continue to be busy and may affect the operation of the next command.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 70 smsc lpc47m172 datasheet 6.20 sense drive status sense drive status obtains drive st atus information. it has not execution phase and goes directly to the result phase from the command phas e. status register 3 contains the drive status information. 6.21 specify the specify command sets the initial values for each of the three internal times. the hut (head unload time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. the srt (step rate time) defines the time interval between adjacent step pulses. note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. the hlt (head load time) defines the time between when the head load signal goes high and the read/write operation starts. the values change with the data rate speed selection and are documented in table 6.26. the values are the same for mfm and fm. dma operation is selected by the nd bit. when nd is ?0 ?, the dma mode is selected. this part does not support non-dma mode. in dma mode, data transfers are signaled by the dma request cycles. 6.22 configure the configure command is issued to select the specia l features of the fdc. a configure command need not be issued if the default values of the fdc meet the system requirements. table 6.26 - drive control delays (ms) hut srt 2m 1m 500k 300k 250k 2m 1m 500k 300k 250k 0 1 .. e f 64 4 .. 56 60 128 8 .. 112 120 256 16 .. 224 240 426 26.7 .. 373 400 512 32 .. 448 480 4 3.75 .. 0.5 0.25 8 7.5 .. 1 0.5 16 15 .. 2 1 26.7 25 .. 3.33 1.67 32 30 .. 4 2 hlt 2m 1m 500k 300k 250k 00 01 02 .. 7f 7f 64 0.5 1 .. 63 63.5 128 1 2 .. 126 127 256 2 4 .. 252 254 426 3.3 6.7 .. 420 423 512 4 8 . 504 508 6.22.1 configure default values eis - no implied seeks efifo - fifo disabled poll - polling enabled fifothr - fifo threshold set to 1 byte
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 71 smsc lpc47m172 datasheet pretrk - pre-compensation set to track 0 eis - enable implied seek. when set to "1", the f dc will perform a seek operation before executing a read or write command. defaults to no implied seek. efifo - a "1" disables the fifo (default). this means data transfers are asked for on a byte-by-byte basis. defaults to "1", fifo disabled. the threshold defaults to "1". poll - disable polling of the drives. defaults to "0", polling enabled. when enabled, a single interrupt is generated after a reset. no polling is performed while the drive head is loaded and the head unload delay has not expired. fifothr - the fifo threshold in the execution phase of read or write commands. this is programmable from 1 to 16 bytes. defaults to one byte. a "00" selects one byte; "0f" selects 16 bytes. pretrk - pre-compensation start track number. progra mmable from track 0 to 255. defaults to track 0. a "00" selects track 0; "ff" selects track 255. 6.23 version the version command checks to see if the controller is an enhanced type or the older type (765a). a value of 90 h is returned as the result byte. 6.24 relative seek the command is coded the same as for seek, except for the msb of the first byte and the dir bit. dir head step direction control rcn relative cylinder number that determines how ma ny tracks to step the head in or out from the current track number. dir action 0 1 step head out step head in the relative seek command differs from the seek co mmand in that it steps t he head the absolute number of tracks specified in the command in stead of making a comparison agains t an internal register. the seek command is good for drives that support a maximum of 256 tracks. relative seeks cannot be overlapped with other relative seeks. only one relative seek can be active at a time. relative seeks may be overlapped with seeks and recalibrates. bit 4 of stat us register 0 (ec) will be set if relative seek attempts to step outward beyond track 0. as an example, assume that a floppy drive has 300 useable tracks. the host needs to read track 300 and the head is on any track (0-255). if a seek command is issued, the head will stop at track 255. if a relative seek command is issued, the fdc will move the head the specified number of tracks, regardless of the internal cylinder position regi ster (but will increment the register). if the head was on track 40 (d), the maximum track that the fdc could position the head on using relative seek will be 295 (d), the initial track + 255 (d). the maximum count that the head can be moved with a single relative seek command is 255 (d). the internal register, pcn, will overflow as the cyli nder number crosses track 255 and will contain 39 (d). the resulting pcn value is thus (rcn + pcn) mod 25 6. functionally, the fdc starts counting from 0 again as the track number goes above 255 (d). it is the user?s responsibility to compensate fdc functions (precompensation track number) when accessing tracks greater than 255. the fdc does not keep track
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 72 smsc lpc47m172 datasheet that it is working in an ?extend ed track area? (greater than 255). any command issued will use the current pcn value except for the recalibrate command, which onl y looks for the track0 signal. recalibrate will return an error if the head is farther than 255 due to its limitation of issuing a maximum of 256 step pulses. the user simply needs to issue a second recalibrate command. the seek command and implied seeks will function correctly within the 44 (d) track (299-255) ar ea of the ?extended track ar ea?. it is the user?s responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. to return to the standard floppy range (0-255) of tr acks, a relative seek should be issued to cross the track 255 boundary. a relative seek can be used instead of the normal seek, but the host is required to calculate the difference between the current head location and the ne w (target) head location. this may require the host to issue a read id command to ensure that the head is physically on the track that software assumes it to be. different fdc commands will return different cylinder results which may be difficult to keep track of with software without the read id command. 6.25 perpendicular mode the perpendicular mode command should be issued pr ior to executing read/write/format commands that access a disk drive with perpendicular recording capability. with this command, the length of the gap2 field and vco enable timing can be altered to acco mmodate the unique requirements of these drives. table 6.27 describes the effects of the wgate and gap bits for the perpendicular mode command. upon a reset, the fdc will default to the conventional mode (wgate = 0, gap = 0). selection of the 500 kbps and 1 mbps perpendicular modes is independent of the actual data rate selected in the data rate select register. the user must ensure that these two data rates remain consistent. the gap2 and vco timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. in the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. this works out to about 38 bytes at a 1 mbps recording density. whenever the write head is enabled by the write gate si gnal, the pre-erase head is also activated at the same time. thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-er ase head since it has not yet been activated. to accommodate this head activation and deactivation time , the gap2 field is expanded to a length of 41 bytes. the format fields table illustrates the change in the gap2 field size for the perpendicular format. on the read back by the fdc, the controller must begin synchronization at the beginni ng of the sync field. for the conventional mode, the internal pll vco is enabled (vcoen) approximately 24 bytes from the start of the gap2 field. but, when the controller operates in the 1 mbps perpendicular mode (wgate = 1, gap = 1), vcoen goes active after 43 bytes to accommodate the increased gap2 field size. for both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in t he presence of motor speed variation. for the write data case, the fdc activates write ga te at the beginning of t he sync field under the conventional mode. the controller then writes a new sync field, data address mark, data field, and crc. with the pre-erase head of the perpendicular drive, the write head must be activated in the gap2 field to insure a proper write of the new sync field. fo r the 1 mbps perpendicular mode (wgate = 1, gap = 1), 38 bytes will be written in the gap2 s pace. since the bit density is proportional to the data rate, 19 bytes will be written in the gap2 field for the 500 k bps perpendicular mode (wgate = 1, gap =0). it should be noted that none of the alterations in gap2 si ze, vco timing, or write gate timing affect normal program flow. the information provided here is just for background purposes and is not needed for normal operation. once the perpendicular mode command is invoked, fdc software behavior from the user standpoint is unchanged.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 73 smsc lpc47m172 datasheet the perpendicular mode command is enhanced to allow specific drives to be designated perpendicular recording drives. this enhancement allows data transfers between conventional and perpendicular drives without having to issue perpendicular mode commands bet ween the accesses of the different drive types, nor having to change write pre-compensation values. when both gap and wgate bits of the perpendicu lar mode command are both programmed to ?0? (conventional mode), then d0, d1, d2, d3, and d4 can be programmed independently to ?1? for that drive to be set automatically to perpendicular mode. in this mode the following set of conditions also apply: 1. the gap2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. the write pre-compensation given to a perpendicular mode drive will be 0ns. 3. for d0-d3 programmed to ?0? for conventional mode drives any data written wi ll be at the currently programmed write pre-compensation. note: bits d0-d3 can only be overwritte n when ow is programmed as a ?1? .if either gap or wgate is a ?1? then d0-d3 are ignored. software and hardware resets have the follow ing effect on the perpendicular mode command: ? ?software? resets (via the dor or dsr registers) will only clear gap and wgate bits to ?0?. d0-d3 are unaffected and retain their previous value. ? ?hardware? resets will clear all bits (gap, wg ate and d0-d3) to ?0?, i. e all conventional mode. table 6.27 - effects of wgate and gap bits wgate gap mode length of gap2 format field portion of gap 2 written by write data operation 0 0 1 1 0 1 0 1 conventional perpendicular (500 kbps) reserved (conventional) perpendicular (1 mbps) 22 bytes 22 bytes 22 bytes 41 bytes 0 bytes 19 bytes 0 bytes 38 bytes 6.26 lock in order to protect systems with long dma latencies ag ainst older application software that can disable the fifo the lock command has been added. this command should only be used by the fdc routines, and application software should refrain from using it. if an application calls for the fifo to be disabled then the configure command should be used. the lock command defines whether the efif o, fifothr, and pretrk parameters of the configure command can be reset by the dor and dsr registers. when the lock bit is set to logic ?1? all subsequent ?software resets by the dor an d dsr registers will not change the previously set parameters to their default values. all ?hardware? reset from the npci_reset pi n will set the lock bit to logic ?0? and return the efifo, fifothr, and pr etrk to their default values. a status byte is returned immediately after issuing a lock command. this byte reflects the value of the lock bit set by the command byte.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 74 smsc lpc47m172 datasheet 6.27 enhanced dumpreg the dumpreg command is designed to support system run-time diagnostics and application software development and debug. to accommodate the lock command and the enhanced perpendicular mode command the eighth byte of the dumpreg command has been modified to contain the additional data from these two commands. 6.27.1 compatibility the lpc47m172 was designed with software compatibility in mind. it is a fully backwards- compatible solution with the older generation 765a/b disk controllers. the fdc also implements on-board registers for compatibility with the ps/2, as well as pc/at and pc/xt, floppy disk controller subsystems. after a hardware reset of the fdc, all registers, functions and enhancements default to a pc/at, ps/2 or ps/2 model 30 compatible operating mode, depending on ho w the ident and mfm bits are configured by the system bios. 6.28 serial port (uart) the lpc47m172 incorporates two full function uarts. they are compatible with the 16450, the 16450 ace registers and the 16c550a. the uarts perform se rial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characte rs. the data rates are independently programmable from 460.8k baud down to 50 baud. the character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioriti zed interrupts. the uarts contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. the uarts are also capable of supporting the midi da ta rate. refer to the configuration registers for information on disabling, power down and changing the base address of the uarts. the interrupt from a uart is enabled by programming out2 of that uart to a logic ?1?. out2 being a logic ?0? disables that uart?s interrupt. the second uart also supports irda, hp-sir, and ask-ir infrared modes of operation. note: input pins of serial port 2 are internally pulled down to vss only until serial port 2 is enabled. once serial port 2 is enabled, the pull-downs are removed until vtr por. 6.28.1 register description addressing of the accessible register s of the serial port is shown below . the base addresses of the serial port is defined by the configuration registers (see ?confi guration? section). the serial port registers are located at sequentially increasing addresses above these base addresses (see table 6.28). table 6.28 - addressing the serial port dlab* a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt i dentification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line status (read/write) x 1 1 0 modem status (read/write)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 75 smsc lpc47m172 datasheet dlab* a2 a1 a0 register name x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write *note : dlab is bit 7 of the line control register the following section describes the operation of the registers. 6.28.2 receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds the received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible. 6.28.3 transmit buffer register (tb) address offset = 0h, dlab = 0, write only this register contains the data byte to be transmitted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. 6.28.4 interrupt enable register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of this register control the enables of the five in terrupt sources of the serial port interrupt. it is possible to to tally disable the interrupt system by resetting bits 0 through 3 of this register. similarly, setting the appropriate bits of this regi ster to a high, selected interrupts can be enabled. disabling the interrupt system inhibi ts the interrupt identif ication register and disables any serial port interrupt out of the lpc47m172. all other system functions operate in their normal manner, including the line status and modem status regi sters. the contents of the inte rrupt enable register are described below. bit 0 this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic ?1?. bit 1 this bit enables the transmitter holding register empty interrupt when set to logic ?1?. bit 2 this bit enables the received line status interrupt when set to logic ?1?. the error sources causing the interrupt are overrun, parity, framing and break. the line status register must be read to determine the source.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 76 smsc lpc47m172 datasheet bit 3 this bit enables the modem status interrupt when set to logic ?1?. this is caused when one of the modem status register bits changes state. bits 4 through 7 these bits are always logic ?0?. 6.28.5 fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only register at the same location as the iir. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. note: dma is not supported. the uart is shadowed in the uart1 fifo control shadow register (power control/runtime register at offset 0x1a). bit 0 setting this bit to a logic ?1? enables both the xmit and rcvr fifos. clearing this bit to a logic ?0? disables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fifo mode to non-fifo (16450) mode, data is automatically cl eared from the fifos. this bit must be a 1 when other bits in this register are written to or they will not be properly programmed. bit 1 setting this bit to a logic ?1? clears all bytes in the rcv r fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 2 setting this bit to a logic ?1? clears all bytes in the xm it fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 3 writing to this bit has no effect on the operation of the uart. the rxrdy and txrdy pins are not available on this chip. bit 4,5 reserved bit 6,7 these bits are used to set the trigger level for the rcvr fifo interrupt. 6.28.6 interrupt identifi cation register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determine the highest priority interrupt and its source. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 77 smsc lpc47m172 datasheet information indicating that a prioritized interrupt is pend ing and the source of that interrupt is stored in the interrupt identification register (refer to interrupt control table). when the cpu accesses the iir, the serial port freezes all interrupts and indicates the highes t priority pending interrupt to the cpu. during this cpu access, even if the serial port records new inte rrupts, the current indicati on does not change until access is completed. the contents of the iir are described below. bit 0 this bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic ?0?, an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic ?1?, no interrupt is pending. bits 1 and 2 these two bits of the iir are used to identify the highest priority interrupt pending as indicated by the interrupt control table. bit 3 in non-fifo mode, this bit is a logic ?0?. in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bits 4 and 5 these bits of the iir are always logic ?0?. bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1. bit 7 bit 6 rcvr fifo trigger level (bytes) 0 0 1 0 1 4 1 0 8 1 1 14 table 6.29 - interrupt control table fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priorit y level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available read receiver buffer or the fifo drops below the trigger level.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 78 smsc lpc47m172 datasheet fifo mode only interrupt identification register interrupt set and reset functions 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register 6.28.7 line control register (lcr) address offset = 3h, dlab = 0, read/write start lsb data 5-8 bits msb parity stop serial data this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: the start, stop and parity bits are not included in the word length. bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits bit 2 this bit specifies the number of stop bits in each tr ansmitted or received serial character. the following table summarizes the information.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 79 smsc lpc47m172 datasheet bit 2 word length number of stop bits 0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. bit 3 parity enable bit. when bit 3 is a logic ?1?, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (the parity bit is used to generate an even or odd number of 1s when the dat a word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic ?1? and bit 4 is a logic ?0?, an odd number of logic ?1??s is transmitted or checked in the data word bits and the parity bit. when bit 3 is a logic ?1? and bit 4 is a logic ?1? an even number of bits is transmitted and checked. bit 5 this bit is the stick parity bit. when parity is enabled it is used in conjunction with bit 4 to select mark or space parity. when lcr bits 3, 4 and 5 are 1 the pa rity bit is transmitted and checked as a 0 (space parity). if bits 3 and 5 are 1 and bit 4 is a 0, then the parity bit is transmitted and checked as 1 (mark parity). if bit 5 is 0 st ick parity is disabled. bit 6 set break control bit. when bit 6 is a logic ?1?, the transmit data output (txd) is forced to the spacing or logic ?0? state and remains there (until reset by a low le vel bit 6) regardless of other transmitter activity. this feature enables the serial port to al ert a terminal in a communications system. bit 7 divisor latch access bit (dlab). it must be set high (l ogic ?1?) to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic ?0?) to access the receiver buffer register, the transmitter holding register , or the interrupt enable register. 6.28.8 modem control register (mcr) address offset = 4h, dlab = x, read/write this 8 bit register controls the interface with the modem or data set (or device emulating a modem). the contents of the modem control re gister are described below. bit 0 this bit controls the data terminal ready (ndtr) outpu t. when bit 0 is set to a logic ?1?, the ndtr output is forced to a logic ?0?. when bit 0 is a logic ?0?, the ndtr output is forced to a logic ?1?. bit 1 this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 80 smsc lpc47m172 datasheet bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic "1", the serial port interrupt outputs are enabled. bit 4 this bit provides the loopback feature for diagnostic te sting of the serial port. when bit 4 is set to logic ?1?, the following occur: 1. the txd is set to the marking state(logic ?1?). 2. the receiver serial input (rxd) is disconnected. 3. the output of the transmitter shift register is ?l ooped back? into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem control output s (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd). 6. the modem control output pins are forced inactive high. 7. data that is transmitted is immediately received. this feature allows the processor to verify the transmi t and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter in terrupts are fully operational. the modem control interrupts are also operational but the interrupts? so urces are now the lower four bits of the modem control register instead of the mo dem control inputs. the interrupts ar e still controlled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic zero. 6.28.9 line status register (lsr) address offset = 5h, dlab = x, read/write bit 0 data ready (dr). it is set to a logic ?1? whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic ?0? by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in the receiver buffer regi ster was not read before the next character was transferred into the register, thereby dest roying the previous character. in fifo mode, an overrun error will occur only when the fifo is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the fifo. the oe indicator is set to a logic ?1? immediately upon detection of an overrun condition, and reset whenever the line status register is read. bit 2 parity error (pe). bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic ?1? upon detection of a parity error and is reset to a logic ?0? whenever the line status r egister is read. in the fifo mode this error is
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 81 smsc lpc47m172 datasheet associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. bit 3 framing error (fe). bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic ?1? whenever the stop bit following the last dat a bit or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic ?0? whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samples this ?start? bit twice and then takes in the ?data?. bit 4 break interrupt (bi). bit 4 is set to a logic ?1? whenev er the received data input is held in the spacing state (logic ?0?) for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the li ne status register. in the fifo mode this error is associated with the particula r character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a break is received, requires the serial data (rxd) to be logic ?1? for at least ? bit time. note : bits 1 through 4 are the error conditions that produc e a receiver line status in terrupt whenever any of the corresponding conditions are detect ed and the interrupt is enabled. bit 5 transmitter holding register empty (thre). bit 5 indica tes that the serial port is ready to accept a new character for transmission. in addition, this bit caus es the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic ?1? when a character is transferred from the transmitter holding re gister into the transmitter shift register. the bit is reset to logic ?0? whenever the cpu loads the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic ?1? whenever the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic ?0? whenever either the thr or tsr contains a data character. bit 6 is a read only bi t. in the fifo mode this bit is set whenever the thr and tsr are both empty, bit 7 this bit is permanently set to logic ?0? in the 450 mode. in the fifo mode, this bit is set to a logic ?1? when there is at least one parity error, fr aming error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. 6.28.10 modem status register (msr) address offset = 6h, dlab = x, read/write this 8 bit register provides the curr ent state of the c ontrol lines from the modem (or peripheral device). in addition to this current state information, four bits of the modem status regist er (msr) provide change information. these bits are set to logic ?1? whenever a control input from the mode m changes state. they are reset to logic ?0? whenever the modem status register is read.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 82 smsc lpc47m172 datasheet bit 0 delta clear to send (dcts). bit 0 indicates that th e ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read. bit 2 trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic ?0? to logic ?1?. bit 3 delta data carrier detect (ddcd). bit 3 indicates that the ndcd inpu t to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logi c ?1?, a modem status interrupt is generated. bit 4 this bit is the complement of the clear to send (ncts) i nput. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to dtr in the mcr. bit 6 this bit is the complement of the ring indicator (nri) input. if bit 4 of the m cr is set to logic ?1?, this bit is equivalent to out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (n dcd) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to out2 in the mcr. 6.28.11 scratchpad register (scr) address offset =7h, dlab =x, read/write this 8 bit read/write register has no effect on the o peration of the serial port. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. 6.29 programmable baud rate gene rator (and divisor latches dlh, dll) the serial port contains a programmable baud rate gener ator that is capable of dividing the internal pll clock by any divisor from 1 to 65535. the internal pll clock is divided down to generate a 1.8462mhz frequency for baud rates less than 38.4k, a 1.8432mhz frequency for 115.2k, a 3.6864mhz frequency for 230.4k and a 7.3728mhz frequency for 460.8k. this output frequency of the baud rate generator is 16x the baud rate. two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16 bi t baud counter is immediately loaded . this prevents long counts on initial load. if a 0 is loaded into the brg registers th e output divides the clock by the number 3. if a 1 is
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 83 smsc lpc47m172 datasheet loaded the output is the inverse of the input oscillator. if a two is loaded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is a 1.8462 mh z clock. table 6.30 shows the baud rates possible. 6.29.1 effect of the reset on register file the reset function (details the effect of the reset input on each of the regist ers of the serial port. 6.29.2 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr bit 0 = ?1?, ier bit 0 = ?1?), rcvr interrupts occur as follows: a. the receive data available interrupt will be is sued when the fifo has reached its programmed trigger level; it is cleared as soon as the fifo drops below its programmed trigger level. b. the iir receive data available indication also occu rs when the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. c. the receiver line status interrupt (iir=06h), has higher priority than the received data available (iir=04h) interrupt. d. the data ready bit (lsr bit 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a. a fifo timeout interrupt occurs if all the following conditions exist: at least one character is in the fifo. the most recent serial character received was long er than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay). the most recent cpu read of the fifo was l onger than 4 continuous character times ago. this will cause a maximum character received to interrupt issued delay of 160 msec at 300 baud with a 12 bit character. b. character times are calculated by using the rcl k input for a clock signal (this makes the delay proportional to the baud rate). c. when a timeout interrupt has occurred it is cl eared and the timer reset when the cpu reads one character from the rcvr fifo. d. when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are en abled (fcr bit 0 = ?1?, ier bit 1 = ?1?), xmit interrupts occur as follows: a. the transmitter holding register interrupt (02h) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. b. the transmitter fifo empty indications will be delay ed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there have not been at least two bytes at the same time in the transmitter fifo since the last thre=1. t he transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 84 smsc lpc47m172 datasheet 6.29.3 fifo polled mode operation with fcr bit 0 = ?1? resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmi tter are controlled separately, either one or both can be in the polled mode of operation. in this mode, the user?s program will check rcvr and xmitter status via the lsr. lsr definitions for the fi fo polled mode are as follows: bit 0=1 as long as there is one byte in the rcvr fifo. bits 1 to 4 specify which error(s) have occurred. c haracter error status is handled the same way as when in the interrupt mode, t he iir is not affected since eir bit 2=0. bit 5 indicates when the xmit fifo is empty. bit 6 indicates that both the xmit fifo and shift register are empty. bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout conditio n indicated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. table 6.30 - baud rates desired baud rate divisor used to generate 16x clock percent error difference between desired and actual 1 high speed bit 2 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1 note 1 : the percentage error for all baud rates, ex cept where indicated otherwise, is 0.2%. note 2 : the high speed bit is located in the device configuration space.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 85 smsc lpc47m172 datasheet table 6.31 - reset function table register/signal reset control reset state interrupt enable register reset all bits low interrupt identification reg. reset bit 0 is high; bits 1 - 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input txd1, txd2 reset high intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/readiir/write thr low out2b reset high rtsb reset high dtrb reset high out1b reset high rcvr fifo reset/ fcr1*fcr0/_fcr0 all bits low xmit fifo reset/ fcr1*fcr0/_fcr0 all bits low
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 86 smsc lpc47m172 datasheet table 32 - register summary for an individual uart channel register address (note 1) register name register symbol bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 addr = 0 dlab = 0 receive buffer register (read only) rbr data bit 0 (note 2) data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 addr = 0 dlab = 0 transmitter holding register (write only) thr da ta bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 addr = 1 dlab = 0 interrupt enable register ier enable received data available interrupt (erdai) enable transmitter holding register empty interrupt (ethrei) enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 0 0 0 0 addr = 2 interrupt ident. register (read only) iir ?0? if interrupt pending interrupt id bit interrupt id bit interrupt id bit (note 6) 0 0 fifos enabled (note 6) fifos enabled (note 6) addr = 2 fifo control register (write only) fcr (note 8) fifo enable rcvr fifo reset xmit fifo reset dma mode select (note 7) reserved reserved rcvr trigger lsb rcvr trigger msb addr = 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) addr = 4 modem control register mcr data terminal ready (dtr) request to send (rts) out1 (note 4) out2 (note 4) loop 0 0 0 addr = 5 line status register lsr data ready (dr) overrun error (oe) parity error (pe) framing error (fe) break interrupt (bi) transmitter holding register (thre) transmitter empty (temt) (note 3) error in rcvr fifo (note 6) addr = 6 modem status register msr delta clear to send (dcts) delta data set ready (ddsr) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) addr = 7 scratch register (note 5) scr bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 addr = 0 dlab = 1 divisor latch (ls) ddl bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 addr = 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 87 smsc/non-smsc register sets ( rev. 01-11-07) datasheet note 1 dlab is bit 7 of the line control register (addr = 3). note 2 bit 0 is the least significant bit. it is the first bit serially transmitted or received. note 3 when operating in the xt mode, this bit will be set any time that the transmitter shift register is empty. note 4 this bit no longer has a pin associated with it. note 5 when operating in the xt mode, th is register is not available. note 6 these bits are always zero in the non-fifo mode. note 7 writing a one to this bit has no effect. dma modes are not supported in this chip. note 8 the uart1 and uart2 fcr?s are shadowed in t he uart1 fifo control shadow register (runtime register at offset 0x20) and uart 2 fifo control shadow register (r untime register at offset 0x21).
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 88 smsc lpc47m172 datasheet chapter 7 notes on serial port operation 7.1 fifo mode operation: 7.1.1 general the rcvr fifo will hold up to 16 bytes regardless of which trigger level is selected. 7.1.2 tx and rx fifo operation the tx portion of the uart transmits data through tx d as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fifo if it currently holds 16 characters . loading to the tx fifo will again be enabled as soon as the next char acter is transferred to the tx shift register. these capabilities account for the largel y autonomous operation of the tx. the uart starts the above operations typically with a tx interrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabled, except in the following instance. assume that the tx fifo is empty and the cpu starts to load it. when the first byte enters the fifo the tx fifo empty interrupt will transition from active to inactive. depending on the execution speed of the service routine software, the uart may be able to transfer this byte from the fifo to the shift register before the cpu loads another byte. if this happens, the tx fifo will be empty again and typically the uart?s interrupt line would transition to the active state. this could cause a system with an interrupt control unit to record a tx fifo empty condition, even though the cpu is currently servicing that interrupt. therefore, after the first byte has been loaded into the fifo the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt delay will remain active until at least two bytes have been loaded into the fifo, concurrently. when the tx fifo empties after this condition, the tx interrupt will be activated without a one character delay . rx support functions and operation are quite different from those described for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the selected interrupt trigger level. at that time if rx interrupts are enabled, the uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more data entering the rx shift register will set the ove rrun error flag. normally, the fifo depth and the programmable trigger levels will give the cpu ample ti me to empty the rx fifo before an overrun occurs. one side-effect of having a rx fifo is that the selected interrupt tri gger level may be above the data level in the fifo. this could occur when data at the end of the block contains fewer bytes than the trigger level. no interrupt would be issued to the cpu and the data would remain in the uart. to prevent the software from having to check for this situation the chip incorporates a timeout interrupt . the timeout interrupt is activated wh en there is a least one byte in the rx fifo, and neither the cpu nor the rx shift register has accessed the rx fifo within 4 character times of the last byte. the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it. these fifo related features allow optimization of cpu/uart transactions and are especially useful given the higher baud rate capability (256 kbaud).
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 89 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.2 infrared interface the infrared interface provides a two-way wireless co mmunications port using infrared as a transmission medium. several ir implementations have been provided for the second uart in this chip, irda, hp-sir and amplitude shift keyed ir. the ir transmission can use the standard uart2 txd2 and rxd2 pins or optional irtx2 and irrx2 pins. these can be se lected through the conf iguration registers. irda 1.0 allows serial communication at baud rates up to 115.2 kbps. each word is sent serially beginning with a zero value start bit. a zero is signaled by se nding a single ir pulse at the beginning of the serial bit time. a one is signaled by sending no ir pulse during the bit time. please refer to the ac timing for the parameters of these pulses and the irda waveform. the amplitude shift keyed ir allows asynchronous serial communication at baud rates up to 19.2k baud. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a 500khz waveform for the duration of the serial bit time. a one is signaled by sending no transmission during the bit time. please refer to the ac timing for the parameters of the ask-ir waveform. if the half duplex option is chosen, there is a time-out when the direction of the transmission is changed. this time-out starts at the last bit transferred duri ng a transmission and blocks t he receiver input until the timeout expires. if the transmit buffer is loaded with mo re data before the time-out expires, the timer is restarted after the new byte is transmitted. if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires afte r the last receive bit has been received. if the start bit of another character is received during this time-out, the timer is restarted after the new character is received. the ir half duplex time-out is programmable via crf2 in logical device 5. this register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. ir transmit pins the following description pertains to the txd2 and irtx2 pins of the lpc47m172. following a vcc por, the txd2 and irtx2 pins will be output and low. they will remain low until one of the following conditions are met: irtx2 pin 1. this pin will remain low following a vcc por until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the ir transmit output of the ircc block. txd2 pin 1. this pin will remain low following a vcc por until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect t he state of the ir trans mit output of the ircc block (if ir is enabled through the ir option register for serial port 2). 2. this pin will remain low following a vcc por until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the stat e of the transmit output of serial port 2. 7.3 parallel port the lpc47m172 incorporates an ibm xt/at compatible parallel port. this supports the optional ps/2 type bi-directional parallel port (spp), the enhanced parallel port (epp) and the exte nded capa bilities port (ecp) parallel port modes. refer to the confi guration registers for information on disabling, power down, changing the base address of the paralle l port, and selecting the mode of operation.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 90 smsc lpc47m172 datasheet the parallel port configuration regist ers are summarized in table 11.2 in the ?configuration? section. the parallel port logical device configuration register s (0xf0 and 0xf1) are defined in table 11.11. the parallel port also incorporates smsc?s chiprote ct circuitry, which prevents possible damage to the parallel port due to printer power-up. the functionality of the parallel port is achieved th rough the use of eight addressable ports, with their associated registers and control gating. the control an d data port are read/write by the cpu, the status port is read/write in the epp mode. the address map of the parallel port is shown below: data port base address + 00h epp data port 0 base address + 04h status port base address + 01h epp data port 1 base address + 05h control port base address + 02h epp data port 2 base address + 06h epp addr port base address + 03h epp data port 3 base address + 07h the bit map of these registers is: d0 d1 d2 d3 d4 d5 d6 d7 note data port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 1 status port tmout 0 0 nerr slct pe nack nbusy 1 control port strobe autofd ninit slc irqe pcd 0 0 1 epp addr port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 2 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 note 1: these registers are available in all modes. note 2: these registers are only available in epp mode.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 91 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 7.1 - parallel port connector host connector smsc pin number standard epp ecp 1 nstrobe nwrite nstrobe 2-9 pd<0:7> pdata<0:7> pdata<0:7> 10 nack intr nack 11 busy nwait busy, periphack(3) 12 pe (user defined) perror, nackreverse (3) 13 slct (user defined) select 14 nalf ndatastb nautofd, hostack(3) 15 nerror (user defined) nfault (1) nperiphrequest (3) 16 ninitp nreset ninit(1) nreverserqst(3) 17 see chapter 3 description of pin functions. nslctin naddrstrb nselectin(1,3) (1) = compatible mode (3) = high speed mode note: for the cable interconnection required for ecp support and the slave connector pin numbers, refer to the ieee 1284 extended capabilities port protocol and isa standard, rev. 1.14, july 14, 1993. this document is av ailable from microsoft. 7.4 ibm xt/at compatible, bi-directional and epp modes 7.4.1 data port address offset = 00h the data port is located at an offset of ?00h? from the base address. the data register is cleared at initialization by reset. during a write operation, the da ta register latches the c ontents of the internal data bus. the contents of this register are buffered (n on inverting) and output onto the pd0 - pd7 ports. during a read operation in spp mode, pd0 - pd7 ports are buffered (not latched) and output to the host cpu. 7.4.2 status port address offset = 01h the status port is located at an offs et of ?01h? from the base address. the contents of this register are latched for the duration of a read cycle. the bi ts of the status port are defined as follows: bit 0 tmout - time out this bit is valid in epp mode only and indicates that a 10 usec time out has occurred on the epp bus. a logic o means that no time out error has occurred; a logic 1 means that a time out error has been detected. this bit is cleared by a reset. if the ti meout_select bit (bit 4 of the parallel port mode register 2, 0xf1 in serial port logical device configurat ion registers) is ?0?, writing a one to this bit clears the tmout status bit. writing a zero to this bit ha s no effect. if the timeout_ select bit (bit 4 of the
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 92 smsc lpc47m172 datasheet parallel port mode register 2, 0xf1 in serial port logical device configuration registers) is ?1?, the tmout bit is cleared on the trailing edge of a read of the epp status register. bits 1, 2 are not implemented as register bits, dur ing a read of the printer status regist er these bits are a low level. bit 3 nerr ? nerror the level on the nerror input is read by the cpu as bit 3 of the printer status register. a logic 0 means an error has been detected; a logi c 1 means no error has been detected. bit 4 slt - printer selected status the level on the slct input is read by the cpu as bi t 4 of the printer status register. a logic 1 means the printer is on line; a logi c 0 means it is not selected. bit 5 pe - paper end the level on the pe input is read by the cpu as bit 5 of the printer status register. a logic 1 indicates a paper end; a logic 0 indicates the presence of paper. bit 6 nack - acknowledge the level on the nack input is read by the cpu as bit 6 of the printer status register. a logic 0 means that the printer has received a character and can now accept another. a logic 1 means that it is still processing the last character or has not received the data. bit 7 nbusy - nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the printer status register. a logic 0 in this bit means that the printer is busy and cannot accept a new character. a logic 1 means that it is ready to accept the next character. 7.4.3 control port address offset = 02h the control port is located at an offs et of ?02h? from the base address. the control register is initialized by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and out put onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output onto t he nautofd output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 ninit - initiate output this bit is output onto the nini tp output without inversion. bit 3 slctin - printer select input this bit is inverted and output onto the nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 93 smsc/non-smsc register sets ( rev. 01-11-07) datasheet bit 4 irqe - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu. an interrupt request is generated on the irq port by a positive going nack input. when the irqe bit is programmed low the irq is disabled. bit 5 pcd - parallel control direction parallel control direction is not valid in printer mo de. in printer mode, the direction is always out regardless of the state of this bit. in bi-directional, epp or ecp mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means t hat the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. 7.4.4 epp address port address offset = 03h the epp address port is located at an o ffset of ?03h? from the base a ddress. the address register is cleared at initialization by reset. during a write operat ion, the contents of the internal data bus db0- db7 are buffered (non invert ing) and output onto the pd0 - pd7 port s. an lpc i/o write cycle causes an epp address write cycle to be performed, during which the data is latched for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports are read. an lpc i/o read cycle causes an epp address read cycle to be performed and the data ou tput to the host cpu, the deassertion of addrstb latches the pdata for the durat ion of the read cycle. this r egister is only available in epp mode. 7.4.5 epp data port 0 address offset = 04h the epp data port 0 is located at an offset of ?04h? fr om the base address. the data register is cleared at initialization by reset. during a write operation, t he contents of the internal data bus db0-db7 are buffered (non inverting) and output onto the pd0 - pd7 ports. an lp c i/o write cycle causes an epp data write cycle to be performed, during which the data is latched for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports are read. an lpc i/o read cycle causes an epp read cycle to be performed and the data output to the hos t cpu, the deassertion of datastb latches the pdata for the duration of the read cycle. th is register is only available in epp mode. 7.4.6 epp data port 1 address offset = 05h the epp data port 1 is located at an offset of ?05h? from the base addr ess. refer to epp data port 0 for a description of operation. this r egister is only available in epp mode. 7.4.7 epp data port 2 address offset = 06h the epp data port 2 is located at an offset of ?06h? from the base addr ess. refer to epp data port 0 for a description of operation. this r egister is only available in epp mode.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 94 smsc lpc47m172 datasheet 7.4.8 epp data port 3 address offset = 07h the epp data port 3 is located at an offset of ?07h? from the base addr ess. refer to epp data port 0 for a description of operation. this r egister is only available in epp mode. 7.5 epp 1.9 operation when the epp mode is selected in the configuration register, the standard and bi-directional modes are also available. if no epp read, write or address cycle is currently executing, t hen the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is cont rolled by pcd of the control port. in epp mode, the system timing is closely coupled to th e epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicate s if more than 10usec have elapsed from the start of the epp cycle to nwait being deasserted (after command). if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0. during an epp cycle, if strobe is active, it override s the epp write signal forcing the pdx bus to always be in a write mode and the nwrite signal to always be asserted. 7.5.1 software constraints before an epp cycle is executed, the software must ens ure that the control regist er bit pcd is a logic ?0? (i.e., a 04h or 05h should be written to the control port). if the user leaves pcd as a logic ?1?, and attempts to perform an epp write, the chip is unable to perform the write (because pcd is a logic ?1?) and will appear to perform an epp read on the parallel bus, no error is indicated. 7.6 epp 1.9 write the timing for a write operation (add ress or data) is shown in timing diagram epp write data or address cycle. the chip inserts wait stat es into the lpc i/o write cycle until it has been determin ed that the write cycle can complete. the write cycle can complete under the following circumstances: 1. if the epp bus is not ready (nwait is active low) when ndatastb or naddrstb goes active then the write can complete when nwait goes inactive high. 2. if the epp bus is ready (nwait is inactive high) t hen the chip must wait for it to go active low before changing the state of ndatastb, nwrite or na ddrstb. the write can complete once nwait is determined inactive. write sequence of operation 1. the host initiates an i/o write cycl e to the selected epp register. 2. if wait is not asserted, the chip must wait until wait is asserted. 3. the chip places address or data on pdata bus, clears pdir, and asserts nwrite. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 5. peripheral deasserts nwait, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. 6. a) the chip deasserts ndatastb or naddrstrb, this marks the beginning of the termination phase. if it has not already done so, the peripheral should latch the information byte now.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 95 smsc/non-smsc register sets ( rev. 01-11-07) datasheet b) the chip latches the data from the internal data bus for the pdata bus and drives the sync that indicates that no more wait states are required followed by the tar to complete the write cycle. 7. peripheral asserts nwait, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 8. chip may modify nwrite and npdata in preparation for the next cycle. 7.7 epp 1.9 read the timing for a read operation (data) is shown in ti ming diagram epp read data cycle. the chip inserts wait states into the lpc i/o read cycl e until it has been determined that the read cycle can complete. the read cycle can complete under the following circumstances: 1. if the epp bus is not ready (nwait is active low) when ndatastb goes active then the read can complete when nwait goes inactive high. 2. if the epp bus is ready (nwait is inactive high) t hen the chip must wait for it to go active low before changing the state of nwrite or before ndatastb goes active. the read can complete once nwait is determined inactive. read sequence of operation 1. the host initiates an i/o read cycle to the selected epp register. 2. if wait is not asserted, the chip must wait until wait is asserted. 3. the chip tri-states the pdata bus and deasserts nwrite. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 5. peripheral drives pdata bus valid. 6. peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 7. a) the chip latches the data from the pdata bus for the intern al data bus and deasserts ndatastb or naddrstrb. this marks the beginning of the termination phase. b) the chip drives the sync that indicates that no more wait states are required and drives valid data onto the lad[3:0] signals, followed by the tar to complete the read cycle. 8. peripheral tri-states the pdata bus and asserts nwait, indicating to the host that the pdata bus is tri- stated. 9. chip may modify nwrite, pdir and npdata in preparation for the next cycle. 7.8 epp 1.7 operation when the epp 1.7 mode is selected in the configurat ion register, the standard and bi-directional modes are also available. if no epp read, wr ite or address cycle is currently ex ecuting, then t he pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is cont rolled by pcd of the control port. in epp mode, the system timing is closely coupled to th e epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicate s if more than 10usec have elapsed from the start of the epp cycle to the end of the cycle. if a time-out occurs, the current epp cycle is abor ted and the time- out condition is indicat ed in status bit 0. 7.8.1 software constraints before an epp cycle is executed, the software must ensure that the control register bits d0, d1 and d3 are set to zero. also, bit d5 (pcd) is a logi c ?0? for an epp write or a logic ?1? for and epp read.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 96 smsc lpc47m172 datasheet 7.9 epp 1.7 write the timing for a write operation (address or data) is shown in timing diagram epp 1.7 write data or address cycle. the chip inserts wa it states into the i/o write cycle when nwait is active low during the epp cycle. this can be used to extend the cycle ti me. the write cycle can complete when nwait is inactive high. write sequence of operation 1. the host sets pdir bit in the control regist er to a logic ?0?. this asserts nwrite. 2. the host initiates an i/o write cy cle to the selected epp register. 3. the chip places address or data on pdata bus. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 5. if nwait is asserted, the chip inserts wait states into i/o write cycle until the peripheral deasserts nwait or a time-out occurs. 6. the chip drives the final sync, deasserts ndat astb or naddrstrb and latches the data from the internal data bus for the pdata bus. 7. chip may modify nwrite, pdir and npdata in preparation of the next cycle. 7.10 epp 1.7 read the timing for a read operation (data) is shown in ti ming diagram epp 1.7 read data cycle. the chip inserts wait states into the i/o r ead cycle when nwait is active low du ring the epp cycle. this can be used to extend the cycle time. the read cycle can complete when nwait is inactive high. read sequence of operation 1. the host sets pdir bit in the control register to a logic ?1?. this deassert s nwrite and tri-states the pdata bus. 2. the host initiates an i/o read cy cle to the selected epp register. 3. chip asserts ndatastb or naddrstrb indicating t hat pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 4. if nwait is asserted, the chip inserts wait states into the i/o r ead cycle until the peripheral deasserts nwait or a time-out occurs. 5. the peripheral drives pdata bus valid. 6. the peripheral deasserts nwait, indicating that pd ata is valid and the chip may begin the termination phase of the cycle. 7. the chip drives the final sync and deasserts ndatastb or naddrstrb. 8. peripheral tri-states the pdata bus. 9. chip may modify nwrite, pdir and npda ta in preparation of the next cycle. table 7.2 - epp pin descriptions epp signal epp name type epp description nwrite nwrite o this signal is active low. it denotes a write operation. pd<0:7> address/data i/o bi -directional epp byte wi de address and data bus. intr interrupt i this signal is active high and positive edge triggered. (pass through with no inversion, same as spp).
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 97 smsc/non-smsc register sets ( rev. 01-11-07) datasheet epp signal epp name type epp description nwait nwait i this signal is active low. it is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. it is driven active as an indication that the device is ready for the next transfer. ndatastb ndata strobe o this signal is active low. it is used to denote data read or write operation. nreset nreset o this signal is active low. when driven active, the epp device is reset to its initial operational mode. naddrstb address strobe o this signal is active low. it is used to denote address read or write operation. pe paper end i same as spp mode. slct printer selected status i same as spp mode. nerr error i same as spp mode. note 1: spp and epp can use 1 common register. note 2: nwrite is the only epp outp ut that can be ov er-ridden by spp control port during an epp cycle. for correct epp read cycles, pcd is required to be a low. 7.10.1 extended capabilities parallel port ecp provides a number of advantages, some of which are listed below. the individual features are explained in greater detail in t he remainder of this section. high performance half-duplex forward and reverse channel interlocked handshake, for fast reliable transfer optional single byte rle compression for improved throughput (64:1) channel addressing for low-cost peripherals maintains link and data layer separation pe rmits the use of active output drivers permits the use of adaptive signal timi ng peer-to-peer capability. 7.10.2 vocabulary the following terms are used in this document: assert: when a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: host to peripheral communication. reverse: peripheral to host communication pword: a port word; equal in size to the width of the lpc interface. for this implementation, pword is always 8 bits. 1 a high level. 0 a low level. these terms may be considered synonymous: periphclk, nack hostack, nautofd periphack, busy nperiphrequest, nfault
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 98 smsc lpc47m172 datasheet nreverserequest, ninit nackreverse, perror xflag, select ecpmode, nselectln hostclk, nstrobe reference document: ieee 1284 extended capabili ties port protocol and isa interface standard , rev 1.14, july 14, 1993. this document is available from microsoft. the bit map of the extended parallel port registers is: d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd 4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nack perror select nfault 0 0 0 1 dcr 0 0 direction ackinten selecti n ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue parallel port irq parallel port dma ecr mode nerrintre n dmaen serviceintr full empty note 1: these registers are available in all modes. note 2: all fifos use one common 16 byte fifo. note 3: the ecp parallel port config reg b reflects the ir q and dma channel selected by the configuration registers. 7.11 ecp implementation standard this specification describes the st andard interface to the extended capabilities port (ecp). all lpc devices supporting ecp must meet t he requirements contained in this section or the port will not be supported by microsoft. for a description of the ec p protocol, please refer to the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.14, july 14, 1993. this document is available from microsoft. 7.11.1 description the port is software and hardware compatible with ex isting parallel ports so that it may be used as a standard lpt port if ecp is not requir ed. the port is designed to be simple and requires a small number of gates to implement. it does not do any ?protocol? negot iation, rather it provid es an automatic high burst-bandwidth channel that supports dma for ecp in both the forward and reverse directions. small fifos are employed in both forward and revers e directions to smooth data flow and improve the maximum bandwidth requirement. the size of the fifo is 16 bytes deep. the port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the port also supports run length encoded (rle) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 99 smsc/non-smsc register sets ( rev. 01-11-07) datasheet next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. hardware support for compression is optional. table 7.3 - ecp pin descriptions name type description nstrobe o during write operations nstrobe registers data or address into the slave on the asserting edge (handshakes with busy). pdata 7:0 i/o contains addr ess or data or rle data. nack i indicates valid data driven by the peripheral when asserted. this signal handshakes with nautofd in reverse. periphack (busy) i this signal deasserts to indicate that the peripheral can accept data. this signal handshakes with nstrobe in the forward direction. in the reverse direction this signal indicates whether the data lines contain ecp command information or data. the peripheral uses this signal to flow control in the forward direction. it is an ?interlocked? handshake with nstrobe. periphack also provides command information in the reverse direction. perror (nackreverse) i used to acknowledge a change in t he direction the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. it is an ?interlocked? handshake with nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select i indicates printer on line. nautofd (hostack) o requests a byte of data from the peripheral when asserted, handshaking with nack in the reverse direction. in the forward direction this signal indicates whether the data lines contain ecp address or data. the host drives this signal to flow control in the reverse direction. it is an ?interlocked? handshake with nack. hostack also provides command information in the forward phase. nfault (nperiphrequest) i generates an error interrupt when asserted. this signal provides a mechanism for peer-to-peer communication. this signal is valid only in the forward direction. during ecp mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. the request is merely a ?hint? to the host; the host has ultimate control over the transfer direction. this signal would be typically used to generate an interrupt to the host cpu. ninit o sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the c hannel in the reverse direction. the peripheral is only allowed to drive the bi-directional data bus while in ecp mode and hostack is low and nselectin is high. nselectin o always deasserted in ecp mode. 7.12 register definitions the register definitions are based on the standard ibm add resses for lpt. all of the standard printer ports are supported. the additional registers attach to an upper bit decode of the st andard lpt port definition to avoid conflict with standard isa devices. the port is equi valent to a generic parallel port interface and may be operated in that mode. the port r egisters vary depending on the mode field in the ecr. the table below lists these dependencies. operation of the devices in modes other t hat those specified is undefined.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 100 smsc lpc47m172 datasheet table 7.4 - ecp register definitions name address (note 1) ecp modes function data +000h r/w 000-001 data register ecpafifo +000h r/w 011 ecp fifo (address) dsr +001h r/w all status register dcr +002h r/w all control register cfifo +400h r/w 010 parallel port data fifo ecpdfifo +400h r/w 011 ecp fifo (data) tfifo +400h r/w 110 test fifo cnfga +400h r 111 configuration register a cnfgb +401h r/w 111 configuration register b ecr +402h r/w all extended control register note 1: these addresses are added to the parallel port base addr ess as selected by configuration register or jumpers. note 2: all addresses are qualified with aen. refer to the aen pin definition. table 7.5 - mode descriptions mode description* 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the configuration registers) 101 reserved 110 test mode 111 configuration mode *refer to ecr register description 7.12.1 data and ecpafifo port address offset = 00h modes 000 and 001 (data port) the data port is located at an offset of ?00h? from the base address. the data register is cleared at initialization by reset. during a wr ite operation, the data register latches the cont ents of the data bus. the contents of this register are buffered (non inverting) a nd output onto the pd0 - pd7 ports. during a read operation, pd0 - pd7 ports are read and output to the host cpu. mode 011 (ecp fifo - address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits this byte to the peri pheral automatically. the o peration of this register is only defined for the forward direction (direction is 0). refer to the ecp parallel port forward timing diagram, located in the timing diagrams section of this data sheet .
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 101 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.12.2 device status register (dsr) address offset = 01h the status port is located at an offset of ?01h? from the base addr ess. bits0 - 2 are not implemented as register bits, during a read of the printer status regist er these bits are a low level. the bits of the status port are defined as follows: bit 3 nfault the level on the nfault input is read by the cpu as bit 3 of the device status register. bit 4 select the level on the select input is read by the cpu as bit 4 of the device status register. bit 5 perror the level on the perror input is read by the cpu as bi t 5 of the device status register. printer status register. bit 6 nack the level on the nack input is read by the cpu as bit 6 of the device status register. bit 7 nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the device status register. 7.12.3 device control register (dcr) address offset = 02h the control register is located at an offset of ?02h? from the base ad dress. the control register is initialized to zero by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and out put onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output onto t he nautofd output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 ninit - initiate output this bit is output onto the nini tp output without inversion. bit 3 selectin this bit is inverted and output onto the nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 ackinten - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu due to a low to hi gh transition on the nack inpu t. refer to the description of the interrupt under operation, interrupts.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 102 smsc lpc47m172 datasheet bit 5 direction if mode=000 or mode=010, this bit has no effect and the direction is always out r egardless of the state of this bit. in all other modes, direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. 7.12.4 cfifo (parallel port data fifo) address offset = 400h mode = 010 bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the standard parallel po rt protocol. transfers to the fi fo are byte aligned. this mode is only defined for the forward direction. 7.12.5 ecpdfifo (ecp data fifo) address offset = 400h mode = 011 bytes written or dmaed from the system to this fif o, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ecp paral lel port protocol. transfers to the fifo are byte aligned. data bytes from the peripheral are read under autom atic hardware handshake from ecp into this fifo when the direction bit is 1. reads or dmas from the fifo will return bytes of ecp data to the system. 7.12.6 tfifo (test fifo mode) address offset = 400h mode = 110 data bytes may be read, written or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the to the parallel port lines using a hardware protocol handshake. however, data in the tfifo may be disp layed on the parallel port data lines. the tfifo will not stall when overwritte n or underrun. if an attempt is made to write data to a full tfifo, the new data is not accepted into the tfifo. if an attempt is made to read dat a from an empty tfifo, the last data byte is re-read again. the full and empty bits must always keep track of the correct fifo state. the tfifo will transfer data at the maximum isa rate so that software may generate performance metrics. the fifo size and interrupt threshold can be determined by writing bytes to the fifo and checking the full and serviceintr bits. the writeintrthreshold can be determined by starting with a full tfifo, setting the direction bit to 0 and emptying it a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 103 smsc/non-smsc register sets ( rev. 01-11-07) datasheet the readintrthreshold can be determined by setting the direction bit to 1 and filling the empty tfifo a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. data bytes are always read from the head of tfifo regar dless of the value of the direction bit. for example if 44h, 33h, 22h is written to the fifo, then reading the tfifo will retu rn 44h, 33h, 22h in the same order as was written. 7.12.7 cnfga (configur ation register a) address offset = 400h mode = 111 this register is a read only register. when read, 10h is returned. this indicates to the system that this is an 8-bit implementation. (pword = 1 byte) 7.12.8 cnfgb (configur ation register b) address offset = 401h mode = 111 bit 7 compress this bit is read only. during a read it is a low level. this means that this chip does not support hardware rle compression. it does support hardware de-compression. bit 6 intrvalue returns the value of the interrupt to determine possible conflicts. bit [5:3] parallel port irq (read-only) to table 7.7 - programming for conf iguration register b (bits 5:3) bits [2:0] parallel port dma (read-only) to table 7.8 - programming for conf iguration register b (bits 2:0) 7.12.9 ecr (extended control register) address offset = 402h mode = all this register controls the ex tended ecp parallel port functions. bits 7,6,5 these bits are read/write and select the mode.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 104 smsc lpc47m172 datasheet bit 4 nerrintren read/write (valid only in ecp mode) 1: disables the interrupt generat ed on the asserting edge of nfault. 0: enables an interrupt pulse on the high to low edge of nfault. note that an interrupt will be generated if nfault is asserted (interrupting) and this bit is written from a 1 to a 0. this prevents interrupts from being lost in the time between the read of the ecr and t he write of the ecr. bit 3 dmaen read/write 1: enables dma (dma starts when serviceintr is 0). 0: disables dma unconditionally. bit 2 serviceintr read/write 1: disables dma and all of the service interrupts. 0: enables one of the following 3 cases of inte rrupts. once one of the 3 service interrupts has occurred serviceintr bit shall be set to a 1 by ha rdware. it must be reset to 0 to re-enable the interrupts. writing this bit to a 1 will not cause an interrupt. case dmaen=1: during dma (this bit is set to a 1 when terminal count is reached). case dmaen=0 direction=0: this bit shall be set to 1 whenever there are writeintrthreshold or more bytes free in the fifo. case dmaen=0 direction=1: this bit shall be set to 1 whenever there are readintrthreshold or more valid bytes to be read from the fifo. bit 1 full read only 1: the fifo cannot accept another byte or the fifo is completely full. 0: the fifo has at least 1 free byte. bit 0 empty read only 1: the fifo is completely empty. 0: the fifo contains at least 1 byte of data.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 105 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 7.6 - extended control register r/w mode 000: standard parallel port mode . in this mode the fifo is reset and common drain drivers are used on the control lines (nstr obe, nautofd, ninit and nselectin). setting the direction bit will not tri-state the output drivers in this mode. 001: ps/2 parallel port mode. same as above except that direction may be used to tri-state the data lines and reading the data register return s the value on the data lines and not the value in the data register. all driver s have active pull-ups (push-pull). 010: parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data is automatically transm itted using the standard parallel port protocol. note that this mode is only useful when dire ction is 0. all drivers have active pull-ups (push-pull). 011: ecp parallel port mode. in the forward dire ction (direction is 0) bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protoc ol. in the reverse direction (direction is 1) bytes are moved from the ecp parallel port and packed into bytes in the ecpdfifo. all drivers have active pull-ups (push-pull). 100: selects epp mode: in this mode, epp is select ed if the epp supported option is selected in parallel port configuration register crf0. all drivers have active pull-ups (push-pull). 101: reserved 110: test mode. in this mode the fifo may be written and read, but the data will not be transmitted on the parallel port. all driv ers have active pull-ups (push-pull). 111: configuration mode. in this mode the confga, confgb registers are accessible at 0x400 and 0x401. all drivers have active pull-ups (push-pull). table 7.7 - programming for configuration register b (bits 5:3) irq selected config reg b bits 5:3 15 110 14 101 11 100 10 011 9 010 7 001 5 111 all others 000 table 7.8 - programming for configuration register b (bits 2:0) dma selected config reg b bits 2:0 3 011 2 010 1 001 all others 000
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 106 smsc lpc47m172 datasheet 7.13 operation 7.13.1 mode switching/software control software will execute p1284 negotiation and all o peration prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port onl y in the data transfer phase (modes 011 or 010). setting the mode to 011 or 010 will cause the hardware to initiate data transfer. if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can only be changed in mode 001. once in an extended forward mode the software should wait for the fifo to be empty before switching back to mode 000 or 001. in this case all control signals will be deasserted before the mode switch. in an ecp reverse mode the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. since t he automatic hardware ecp reverse ha ndshake only cares about the state of the fifo it may have acquired extr a data which will be discarded. it may in fact be in the middle of a transfer when the mode is changed back to 000 or 00 1. in this case the port will deassert nautofd independent of the state of the tr ansfer. the design shall not cause glitches on the handshake signals if the software meets the constraints above. 7.14 ecp operation prior to ecp operation the host must negotiate on the par allel port to determine if the peripheral supports the ecp protocol. this is a somewhat complex negotiation carried out under program control in mode 000. after negotiation, it is necessary to initialize some of the port bits. the following are required: set direction = 0, enabling the drivers. set strobe = 0, causing the nstrobe sign al to default to the deasserted state. set autofd = 0, causing the nautofd si gnal to default to the deasserted state. set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent au tomatically by writing the ecpafifo or ecpdfifo respectively. note that all fifo data transfers are byte wide and byte aligned. address/rle transfers are byte-wide and only allowed in the forward direction. the host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. when direction is 1 the hardware shall handshake for each ecp read data byte and attempt to fill the fifo. bytes may then be read from the ecpdfifo as long as it is not empty. ecp transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 107 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.15 termination from ecp mode termination from ecp mode is similar to the termination from nibble/byte modes. the host is permitted to terminate from ecp mode only in specific well-defin ed states. the termination can only be executed while the bus is in the forward direction. to terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. 7.16 command/data ecp mode supports two advanced features to improv e the effectiveness of the protocol for some applications. the features are implemented by allo wing the transfer of normal 8 bit data or 8 bit commands. when in the forward direction, normal data is transferred when hostack is high and an 8 bit command is transferred when hostack is low. the most significant bit of the command indicates whet her it is a run-length count (for compression) or a channel address. when in the reverse direction, normal data is transfe rred when periphack is high and an 8 bit command is transferred when periphack is low. the most signifi cant bit of the command is always zero. reverse channel addresses are seldom used and may not be supported in hardware. table 7.9 - channel/data commands supported in ecp mode forward channel commands (hostack low) reverse channel commands (peripack low) d7 d[6:0] 0 run-length count (0-127) (mode 0011 0x00 only) 1 channel address (0-127) 7.17 data compression the ecp port supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. run length encoded (rle) compression in hardware is not supported. to transfer compressed data in ecp mode, the compre ssion count is written to the ecpafifo and the data byte is written to the ecpdfifo. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. w hen a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. a run-length count of zero specifies that only one byte of data is r epresented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. to prevent data expansion, however, run-length counts of zero should be avoided. 7.18 pin definition the drivers for nstrobe, nautofd, ninit and nselectin are open-drain in mode 000 and are push-pull in all other modes.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 108 smsc lpc47m172 datasheet 7.19 lpc connections the interface can never stall causing the host to hang. the width of data tr ansfers is strictly controlled on an i/o address basis per this specification. a ll fifo-dma transfers are byte wide, byte ali gned and end on a byte boundary. (the pword value can be obtained by reading configuration register a, cnfga, described in the next section). single byte wide tr ansfers are always possible with standard or ps/2 mode using program control of the control signals. 7.20 interrupts the interrupts are enabled by servic eintr in the ecr register. serviceintr = 1 disables the dma and all of the service interrupts. serviceintr = 0 enables the selected interrupt condition. if the interrupting condition is valid, then the interrupts generated immediately when this bit is changed from a 1 to a 0. this can occur during programmed i/o if the number of bytes removed or added from/to the fifo does not cross the threshold. an interrupt is generated when: 1. for dma transfers: when serviceintr is 0, dm aen is 1 and the dma tc cycle is received. 2. for programmed i/o: a. when serviceintr is 0, dmaen is 0, direction is 0 and there are writeintrthreshold or more free bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are writeintrthr eshold or more free bytes in the fifo. b. when serviceintr is 0, dmaen is 0, direction is 1 and there are readintrthreshold or more bytes in the fifo. also, an interrupt is generated when se rviceintr is cleared to 0 whenever there are readintrthreshold or more bytes in the fifo. 3. when nerrintren is 0 and nfault trans itions from high to low or when nerrintren is set from 1 to 0 and nfault is asserted. 4. when ackinten is 1 and the nack signal transitions from a low to a high. 7.21 fifo operation the fifo threshold is set in the chip configuration regi sters. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode as indicated by the sele cted mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. (fifo test mode will be addressed separately.) after a reset, the fifo is disabled. each data byte is transferred by a programmed i/o cycle or dma cycle depending on t he selection of dma or programmed i/o mode. the following paragraphs detail the operation of the fifo flow control. in these descriptions, ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host must be very responsive to the service request. this is the desired case for use with a ?fast? system. a high value of threshold (i.e. 12) is used with a ?sluggish? system by affording a long latency period after a service request, but results in more frequent service requests.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 109 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.21.1 dma transfers dma transfers are always to or from the ecpdfifo , tfifo or cfifo. dma utilizes the standard pc dma services. to use the dma transfers, the host first sets up the direction and state as in the programmed i/o case. then it programs the dma contro ller in the host with the desired count and memory address. lastly it sets dmaen to 1 and serviceintr to 0. the ecp requests dma transfers from the host by encoding the nldrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and serviceintr is asserted, disabling dma. in order to prevent possible blocking of refresh requests a dma cycle shall not be requested for more than 32 dma cycles in a row. the fifo is enabled directly by the host initiating a dma cycle for the requested channel, and addresses need not be valid. an interrupt is generated when a tc cycle is received. (note: the only way to properly terminate dma transfers is with a tc cycle.) dma may be disabled in the middle of a transfer by first disabling the host dma controller. then setting serviceintr to 1, followed by setting dmaen to 0, and waiting for the fifo to become empty or full. restarting the dma is accomplished by enabling dma in the host, setting dmaen to 1, followed by setting serviceintr to 0. 7.21.2 dma mode - transfers fr om the fifo to the host (note: in the reverse mode, the periphe ral may not continue to fill the fifo if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) the ecp requests a dma cycle whenever there is data in the fifo. the dma controller must respond to the request by reading data from the fifo. the ecp stops requesting dma cycles when the fifo becomes empty or when a tc cycle is received, indicati ng that no more data is required. if the ecp stops requesting dma cycles due to the fifo going empty, then a dma cycle is requested again as soon as there is one byte in the fifo. if the ecp stops requ esting dma cycles due to the tc cycle, then a dma cycle is requested again when there is one byte in the fifo, and serviceintr has been re-enabled. 7.21.3 programmed i/o mode or non-dma mode the ecp or parallel port fifos ma y also be operated using interrupt driven programmed i/o. software can determine the writeintrthreshold , readintrthreshold, and fifo depth by accessing the fifo in test mode. programmed i/o transfers are to the ec pdfifo at 400h and ecpafifo at 00 0h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. to use the progr ammed i/o transfers, the host first sets up the direction and state, sets dmae n to 0 and serviceintr to 0. the ecp requests programmed i/o trans fers from the host by activati ng the interrup t. the programmed i/o will empty or fill the fifo using the appropriate di rection and mode. note: a threshold of 16 is equivalent to a threshold of 15. these two cases are treated the same. 7.21.4 programmed i/o - transfers from the fifo to the host in the reverse direction an interrupt occurs when serv iceintr is 0 and readintrthreshold bytes are available in the fifo. if at this time the fifo is full it can be emptied completely in a single burst, otherwise readintrthreshold bytes may be read from the fifo in a single burst. readintrthreshold =(16-) data bytes in fifo
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 110 smsc lpc47m172 datasheet an interrupt is generated when serviceintr is 0 and the nu mber of bytes in the fifo is greater than or equal to (16-). (if the threshold = 12, then t he interrupt is set whenever there are 4-16 bytes in the fifo). the host must respond to the request by readi ng data from the fifo. this process is repeated until the last byte is transferred out of the fifo. if at this time the fifo is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the fifo in a single burst. 7.21.5 programmed i/o - transfers from the host to the fifo in the forward direction an interrupt occurs when serv iceintr is 0 and there are wr iteintrthreshold or more bytes free in the fifo. at this time if the fifo is em pty it can be filled with a single burst before the empty bit needs to be re-read. otherwise it may be filled with writeintrthreshold bytes. writeintrthreshold = (16-) free bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is less than or equal to . (if the threshold = 12, t hen the interrupt is set whenever ther e are 12 or less bytes of data in the fifo.) the host must respond to the request by writ ing data to the fifo. if at this time the fifo is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the fifo in a single burst. this process is repeated until the last byte is transferred into the fifo. 7.22 power management direct power management capability is provided for the following logical devices: floppy disk, uart, and the parallel port. direct power management is controlle d by cr22. refer to cr22 in table 11.3 for more information. note on fdc direct powerdown: th e direct powerdown mode requires at least 8us delay at 250k bits/sec configuration and 4us de lay at 500k bits/sec. the dela y should be added so that the internal microcontroller can prepare itself to accept commands. 7.23 serial irq the lpc47m172 supports the serial interrupt to transm it interrupt information to the host system. the serial interrupt scheme adheres to the serial ir q specification for pci systems, version 6.0. 7.23.1 timing diagrams for ser_irq cycle a) start frame timing with source sampled a low pulse on irq1 rt s rt s ser_irq pci_clk host controller irq1 irq1 drive source rt none irq0 frame irq1 frame s rt irq2 frame none start start frame h sl or h 1 note: h=host control; r=recovery; t=turn -around; sl=slave control; s=sample
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 111 smsc/non-smsc register sets ( rev. 01-11-07) datasheet note 1: start frame pulse can be 4-8 clo cks wide depending on the location of the de vice in the pci bridge hierarchy in a synchronous bridge design. b) stop frame timing with host using 17 ser_irq sampling period s rt s ser_irq pci_clk host controller irq15 driver rt none irq14 irq15 s rt iochck# none stop rt stop frame h i start next cycle 1 2 3 frame frame frame note: h=host control; r=recovery; t= turn-around; s=sample; i=idle note 1: the next ser_irq cycle?s start frame pulse may or may not start immediately after the turn-around clock of the stop frame. note 2: there may be none, one or more idle states during the stop frame. note 3: stop pulse is 2 clocks wide for quiet mode, 3 clocks wide for continuous mode. 7.23.2 ser_irq cycle control there are two modes of operati on for the ser_irq start frame: 1) quiet (active) mode : any device may initiate a start frame by driving the ser_irq low for one clock, while the ser_irq is idle. after driving low for one clock the ser_irq must immediately be tri-stated without at any time driving high. a start frame ma y not be initiated while the ser_irq is active. the ser_irq is idle between stop and start frames. the ser_irq is active between start and stop frames. this mode of operation allo ws the ser_irq to be idle when t here are no irq/data transitions which should be most of the time. once a start frame has been initia ted the host controller will take ov er driving the ser_irq low in the next clock and will continue driving the ser_irq low for a programmable period of three to seven clocks. this makes a total low pulse width of four to eight cl ocks. finally, the host controller will drive the ser_irq back high for one clock, then tri-state. if lpc47m172 detects any transition on an irq/data line for which it is responsible, it initiates a start frame in order to update the host c ontroller unless the ser_irq is alr eady in an ser_irq cycle and the irq/data transition can be delivered in that ser_irq cycle 2) continuous (idle) mode : only the host controller can initia te a start frame to update irq/data line information. all other ser_irq agents become passive and may not initiate a st art frame. ser_irq will be driven low for four to eight clocks by host contro ller. this mode has two functions. it can be used to stop or idle the ser_irq or the host controller can operate ser_irq in a continuous mode by initiating a start frame at the end of every stop frame. an ser_irq mode transition can only occur durin g the stop frame. upon reset, ser_irq bus is defaulted to continuous mode, therefore only the host controller can in itiate the first start frame. slaves must continuously sample the stop frames pulse wi dth to determine the next ser_irq cycle?s mode.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 112 smsc lpc47m172 datasheet 7.23.3 ser_irq data frame once a start frame has been initiated, the lpc47m17 2 will watch for the rising edge of the start pulse and start counting irq/data frames from there. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase the lpc47m172 drives the ser_irq low, if and only if, its last detected irq/data valu e was low. if its detected irq/data value is high, ser_irq is left tri-stated. during the recovery phase the lpc47m172 drives the ser_irq high, if and only if, it had driven the ser_irq low during the prev ious sample phase. during the turn-around phase the lpc47m172 tri-states the ser_i rq. the lpc47m172 drives the ser_irq line low at the appropriate sample point if its associated irq/data line is low, regardless of which device in itiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times thre e, minus one. (e.g. the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17 th clock after the rising edge of the start pulse). ser_irq sampling periods ser_irq period signal sampled # of clocks past start 1 not used 2 2 irq1 5 3 irq2 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 ser_irq period 14 is used to transfer irq13. logica l devices fdc, parallel port, serial port, and keyboard have irq13 as a choice for their primary interrupt. 7.23.4 stop cycle control once all irq/data frames have completed the host contro ller will terminate ser_irq activity by initiating a stop frame. only the host cont roller can initiate the stop frame. a stop frame is indicated when the ser_irq is low for two or three clocks. if the stop frame?s low time is two clocks then the next ser_irq cycle?s sampled mode is the quiet mode; and any ser_irq device may initiate a start frame in the second clock or more after the rising edge of the st op frame?s pulse. if the stop frame?s low time is three clocks then the next ser_irq cycle?s sampled mode is the continuous mode; and only the host controller may initiate a start frame in the second cl ock or more after the rising edge of the stop frame?s pulse.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 113 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.23.5 latency latency for irq/data updates over the ser_irq bus in bridge-less systems with the minimum host supported irq/data frames of seventeen, will rang e up to 96 clocks (3.84 s with a 25mhz pci bus or 2.88us with a 33mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. 7.23.6 eoi/isr read latency any serialized irq scheme has a potent ial implementation issue related to irq latency. ir q latency could cause an eoi or isr read to precede an irq transitio n that it should have followed. this could cause a system fault. the host interrupt controller is resp onsible for ensuring that these latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the ser_irq cycle latency in order to ensure that these event s do not occur out of order. 7.23.7 ac/dc speci fication issue all ser_irq agents must drive / sample ser_irq sy nchronously related to the rising edge of pci bus clock. the ser_irq pin uses the elec trical specification of pci bus. electrical parameters will follow pci spec. section 4, sustained tri-state. 7.23.8 reset and initialization the ser_irq bus uses npci_reset as its reset signal. t he ser_irq pin is tri-stated by all agents while npci_reset is active. with reset, ser_irq slav es are put into the (continuous) idle mode. the host controller is responsible for starting the init ial ser_irq cycle to collect system?s irq/data default values. the system then follows with the continuous /quiet mode protocol (stop frame pulse width) for subsequent ser_irq cycles. it is ho st controller?s responsibility to provide the default values to 8259?s and other system logic before the first ser_irq cy cle is performed. for ser_irq system suspend, insertion, or removal application, the host controller should be progr ammed into continuous (idle) mode first. this is to guarantee ser_irq bus is in id le state before the system configuration changes. 7.24 interrupt generating registers the lpc47m172 contains on-chip interrupt generating re gisters to enable external software to generate irq1 through irq15 on the serial irq interface. these registers, in t_gen1 and int_gen2, are located in the power control block/runtime register block, at offsets 0x1b and 0x1c, respectively, from the base address setting (set at index 0x60 and 0x61 configur ation registers). see chapter 8 power control runtime registers and chapter 10 runtime register block runtime registers. registers int_gen1 and int_gen2 are enabled to output to the serial irq stream by setting power control block configuration register, at index 0xf1, bit [0] to ?1?. when bit [0] is set to ?0?, int_gen1 and int_gen2 are prevented from outputting to the serial irq stream. writing bits 0 through 7 to ?0? in registers int_gen1 and int_gen2 enable the corresponding interrupt (int1 through int15) to be asserted (made active) in t he serial irq stream. producing an interrupt in the serial irq stream by writing these bits to ?0? overri des other interrupt sources for the serial irq stream. no other functional logic in the lpc47m172 sets bits in these registers. the asserted interrupt in the serial irq stream from registers int_gen1 and int_gen2 is removed by writing the corresponding bit to ?1?.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 114 smsc lpc47m172 datasheet 7.25 8042 keyboard controller description the lpc47m172 is a super i/o and universal keyboard c ontroller that is design ed for intelligent keyboard management in desktop computer applications. the universal keyboard controller uses an 8042 microcontroller cpu core. this section concentrates on the lpc47m172 enhancements to the 8042. for general information about the 8042, refer to the ?hardw are description of the 8042? in the 8-bit embedded controller handbook. 8042a p27 p10 p26 tst0 p23 tst1 p22 p11 kdat kclk mclk mdat keyboard and mouse interface ls05 kirq is the keyboard irq mirq is the mouse irq port 21 is used to create a gat ea20 signal from the lpc47m172. 7.25.1 keyboard interface the lpc47m172 lpc interface is functionally compatible with the 8042 style host interface. it consists of the d0-7 data signals; the read and write signals and the status regist er, input data register, and output data register. table 7.10 shows how the interface dec odes the control signals. in addition to the above signals, the host interface includes keyboard and mouse irqs. table 7.10 - i/o address map address command block function (note 1) 0x60 write kdata keyboard data write (c/d=0) read kdata keyboard data read 0x64 write kdctl keyboard command write (c/d=1) read kdctl keyboard status read note 1: these registers consist of three separate 8 bit r egisters. status, data/command write and data read.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 115 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.25.2 keyboard data write this is an 8 bit write only register. when written, the c/d status bit of the status register is cleared to zero and the ibf bit is set. 7.25.3 keyboard data read this is an 8 bit read only register. if enabled by ?enable flags?, when read, the kirq output is cleared and the obf flag in the status register is cleared. if not enabled, the kirq and/or auxobf1 must be cleared in software. 7.25.4 keyboard command write this is an 8 bit write only register. when written, the c/d status bit of the status register is set to one and the ibf bit is set. 7.25.5 keyboard status read this is an 8 bit read only register. refer to the de scription of the status register for more information. 7.25.6 cpu-to-host communication the lpc47m172 cpu can write to the output data regist er via register dbb. a write to this register automatically sets bit 0 (obf) in t he status register. see table 7.11. table 7.11 - host interface flags 8042 instruction flag out dbb set obf, and, if enabled, the kirq output signal goes high 7.25.7 host-to-cpu communication the host system can send both commands and data to th e input data register. the cpu differentiates between commands and data by reading the value of bit 3 of the status register . when bit 3 is ?1?, the cpu interprets the register contents as a command. when bit 3 is ?0?, the cpu interprets the register contents as data. during a host write operation, bit 3 is set to ?1? if sa2 = 1 or reset to ?0? if sa2 = 0. 7.25.8 kirq if ?en flags? has been executed and p24 is set to a one: the obf flag is gated onto kirq. the kirq signal can be connected to system interrupt to signi fy that the lpc47m172 cpu has written to the output data register via ?out dbb,a?. if p24 is set to a zero , kirq is forced low. on power-up, after a valid rst pulse has been delivered to the device, kirq is reset to 0. kirq will normally refl ects the status of writes ?dbb?. (kirq is normally selected as irq1 for keyboard support.) if ?en flags? has not been executed: kirq can be cont rolled by writing to p24. writing a zero to p24 forces kirq low; a high forces kirq high.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 116 smsc lpc47m172 datasheet 7.25.9 mirq if ?en flags? has been executed and p25 is set to a one:; ibf is inverted and gated onto mirq. the mirq signal can be connected to system interrupt to signify that the lpc 47m172 cpu has read the dbb register. if ?en flags? has not been executed, mirq is controlled by p 25, writing a zero to p25 forces mirq low, a high forces mirq high. (mirq is normally selected as irq12 for mouse support). gate a20 a general purpose p21 is used as a software controlled gate a20 or user defined output. 8042 pins the 8042 functions p17, p16 and p12 are not supported in lpc47m172. 7.25.10 external keyboard and mouse interface industry-standard pc-at-compatible keyboards employ a two-wire, bidirectional ttl interface for data transmission. several sources also supply ps/2 mouse products that employ the same type of interface. to facilitate system expansio n, the lpc47m172 provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. the lpc47m172 has four high-drive, open-drain output, bidirectional po rt pins that can be used for external serial interfaces, such as external keyboa rd and ps/2-type mouse interfaces. they are kclk, kdat, mclk, and mdat. p26 is inverted and output as kclk. the kclk pin is connected to test0. p27 is inverted and output as kdat. the kdat pin is connected to p10. p23 is inverted and output as mclk. the mclk pin is connected to test1. p22 is inverted and output as mdat. the mdat pin is connected to p11. note: external pull-ups may be required. 7.25.11 keyboard power management the keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown mode. in soft powerdown mode, the clock to the al u is stopped but the timer/ counter and interrupts are still active. in hard power down mode the clock to the 8042 is stopped. 7.25.12 soft power down mode this mode is entered by executing a halt instruction. the executi on of program code is halted until either reset is driven active or a data byte is wri tten to the dbbin register by a master cpu. if this mode is exited using the interrupt, and the ibf interrupt is enabled, then program execution resumes with a call to the interrupt routin e, otherwise the next instruction is ex ecuted. if it is exit ed using reset then a normal reset sequence is initiated and program exec ution starts from program memory location 0. 7.25.13 hard power down mode this mode is entered by executing a stop instruction. the oscillator is stopped by disabling the oscillator driver cell. when either reset is driven active or a data byte is written to the dbbin register by a master cpu, this mode will be exited (as above) . however, as the oscillator cell will require an initialization time, either reset must be held active for sufficient time to allow the oscillator to stabilize. program execution will resume as above.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 117 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.25.14 interrupts the lpc47m172 provides the two 8042 interr upts: ibf and the timer/counter overflow. 7.25.15 memory configurations the lpc47m172 provides 2k of on-chip rom and 256 bytes of on-chip ram. 7.25.16 register definitions host i/f data register the input data register and output data register are each 8 bits wide. a writ e to this 8 bit register will load the keyboard data read buffer, set the obf flag and se t the kirq output if enab led. a read of this register will read the data from t he keyboard data or command write buffer and clear the ibf flag. refer to the kirq and status register de scriptions for more information. host i/f status register the status register is 8 bits wide. table 7.12 shows the contents of the status register. table 7.12 - status register d7 d6 d5 d4 d3 d2 d1 d0 ud ud ud ud c/d ud ibf obf status register this register is cleared on a reset. this register is read-only for the host and read/write by the lpc47m172 cpu. ud writable by lpc47m172 cpu. these bits are user-definable. c/d (command data)-this bit specifies whether the in put data register contai ns data or a command (0 = data, 1 = command). during a host data/command write operation, this bit is set to ?1? if sa2 = 1 or reset to ?0? if sa2 = 0. ibf (input buffer full)- this flag is set to 1 whenever the host system writes data into the input data register. setting this flag activates the lpc47m 172 cpu?s nibf (mirq) inte rrupt if enabled. when the lpc47m172 cpu reads the input data register (dbb), this bit is automatically reset and the interrupt is cleared. there is no output pin associated with this internal signal. obf (output buffer full) - this flag is set to wh enever the lpc47m172 cpu wr ite to the output data register (dbb). when the host system reads the output data register, this bit is automatically reset.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 118 smsc lpc47m172 datasheet 7.25.17 external clock signal the lpc47m172 keyboard controller clock source is a 12 mhz clock generated from a 14.318 mhz clock. the reset pulse must last for at least 24 16 mhz cl ock periods. the pulse-width requirement applies to both internally (vcc por) and externally generated re set signals. in powerdown mode, the external clock signal is not loaded by the chip. 7.25.18 default reset conditions the lpc47m172 has one source of hardware reset: an external reset via the npci_reset pin. refer to table 7.13 for the effect of each type of reset on the internal registers. table 7.13 - keyboard and mouse pin/register reset values description hardware reset (npci_reset) kclk low kdat low mclk low mdat low host i/f data reg n/a host i/f status reg 00h note: n/a: not applicable 7.25.19 gatea20 and keyboard reset the lpc47m172 provides two options for gatea20 and keyboard reset: 8042 software generated gatea20 and kreset and port 92 fast gatea20 and kreset. 7.26 port 92 fast gatea20 and keyboard reset 7.26.1 port 92 register this port can only be read or written if port 92 has been enabled via bit 2 of the krst_ga20 register (keyboard logical device, 0xf0) set to 1. this register is used to support the alternate rese t (nalt_rst) and alternate a20 (alt_a20) functions.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 119 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 7.14 - keyboard port 92 register name port 92 location 92h default value 24h attribute read/write size 8 bits port 92 register bit function 7:6 reserved. returns 00 when read 5 reserved. returns a 1 when read 4 reserved. returns a 0 when read 3 reserved. returns a 0 when read 2 reserved. returns a 1 when read 1 alt_a20 signal control. writing a 0 to this bit causes the alt_a20 signal to be driven low. writing a 1 to this bit causes the alt_a20 signal to be driven high. 0 alternate system reset. this read/write bit provides an alternate system reset function. this function provides an alte rnate means to reset the system cpu to effect a mode switch from protected vi rtual address mode to the real address mode. this provides a faster means of reset than is provided by the keyboard controller. this bit is set to a 0 by a system reset. writing a 1 to this bit will cause the nalt_rst signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. before another nalt_rst pulse can be generated, this bit must be written back to a 0. bit 0 of port 92, which generates the nalt_rst signal, is used to reset the cpu under program control. this signal is and?ed together with the reset signal (krst) from the keyboard controller to provide a software means of resetting the cpu. this provides a faster means of reset than is provided by the keyboard controller. writing a 1 to bit 0 in the port 92 register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. before another nalt_rst pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to port 92. upon reset, this signal is driven inactive high (bit 0 in the port 92 register is set to 0). if port 92 is enabled, i.e., bit 2 of krst_ga20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the port 92 register and this pulse is and?ed with the pulse generated from the 8042. this pulse is output on pin nkbdrst and its polarity is cont rolled by the gpi/o pol arity configuration.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 120 smsc lpc47m172 datasheet 8042 p92 pulse gen nkbdrst krst_ga20 configuration register bit 2 bit 0 p20 krst nalt_rst 6us 14us ~~ 6us 14us ~ ~ note: when port 92 is disabled, writes are ignored and reads return undefined values. figure 7.1 - nkbdrst circuit bit 1 of port 92, the alt_a20 signal, is used to fo rce na20m to the cpu low for support of real mode compatible software. this signal is or?ed with t he a20gate signal from the keyboard controller and nkbdrst to control the na20m input of the cpu. writ ing a 0 to bit 1 of the port 92 register forces alt_a20 low. alt_a20 low drives na20m to the cpu low, if a20gate from t he keyboard controller is also low. writing a 1 to bit 1 of the port 92 regist er forces alt_a20 high. alt_a20 high drives na20m to the cpu high, regardless of the state of a20gate from the keyboard controller. upon reset, this signal is driven low. table 7.15 - na20m truth table 8042 p21 alt_a20 system na20m 0 0 0 0 1 1 1 0 1 1 1 1 latches on keyboard and mouse irqs the implementation of the latches on the key board and mouse interrupts is shown following.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 121 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 8042 vcc dq kint kint new rd 60 clr klatch bit figure 7.2 - keyboard latch 8042 vcc dq mint mint new rd 60 clr mlatch bit figure 7.3 - mouse latch the klatch and mlatch bits are located in the krst_ga20 register, in keyboard logical device at 0xf0.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 122 smsc lpc47m172 datasheet these bits are defined as follows: bit[4]: mlatch ? mouse interrupt latch control bit. 0=mint is the 8042 mint anded with latched mint (default), 1=mint is the latched 8042 mint. bit[3]: klatch ? keyboard interrupt latch control bit. 0=kint is the 8042 kint anded with latched kint (default), 1=kint is the latched 8042 kint. see the ?configuration? section fo r a description of this register. 7.26.2 keyboard and mouse pme generation the lpc47m172 sets the associated pme status bits when the following conditions occur: ? keyboard interrupt ? mouse interrupt ? active edge on keyboard data signal (kdat) ? active edge on mouse data signal (mdat) these events can cause a pme to be generated if the associated pme wa ke enable register bit and the global pme_en bit are set. refer to the pme support section for more details on the pme interface logic and refer to the runtime register block runtime r egisters sections for details on the pme status and enable registers. the keyboard interrupt and mouse interrupt pmes can be generated when the part is powered by vcc. the keyboard data and mouse data pmes can be generated both when the part is powered by vcc, and when the part is powered by vtr (vcc=0). when using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals (kclk, kdat, mclk, mdat) from the 8042 prior to entering certain system sleep states. this is due to the fact that the nor mal operation of the 8042 can prevent the system from entering a sleep state or trigger false pme events. the lpc47m172 has a mo de to select the isolation of keyboard and mouse clock and data signals by hardware when the nlpcpd sig nal is active and/or when the isolation bits are set by software. the mode allows the keyboard and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. the mo de may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 bef ore entering a system sl eep state. this mode applies to anykey wakeup from s3, but it does not a ffect wake from s1. the mode is selected by iso_mode bit in the keyboard logical device configur ation register 0xf0. the iso_mode bit is defined as follows: bit[7] iso_mode in krst_ga20 register (0xf0) 0: mode 1 (default) ? isolate the 8042 in hardwar e while the nlpcpd signal is active or when the keyboard and mouse isolation bits are set by software. 1: mode 2 ? keyboard and mouse isolation bits set by software only. (note: the input path to the 8042 is also isolated while the nlpcpd signal is active.) the bits used to isolate the keyboard and mouse sign als from the 8042 are located in keyboard logical device, register 0xf0 (krst_ga20) and are defined below. these bits reset on vtr por only. bit[6] m_iso. enables/disables isolation of mouse signals into 8042. does not affect the mdat signal to the mouse wakeup (pme) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 123 smsc/non-smsc register sets ( rev. 01-11-07) datasheet bit[5] k_iso. enables/disables isolation of key board signals into 8042. does not affect the kdat signal to the keyboard wakeup (pme) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 see the smsc application note titled ?using t he enhanced keyboard and mouse wakeup feature in smsc super i/o parts? for more information on isolation bits. if either of the isolation bits (m_iso , k_sio) is set prior to entering a sleep state where vcc goes inactive (s3-s5), then the 8042 must be rese t upon exiting the sleep mode. writ e 0x40 to global configuration register 0x2c to reset the 8042. the 8042 must then be taken out of reset by writing 0x00 to register 0x2c since the bit that resets the 8042 is not self-clearing. caution: bit 6 of configuration register 0x2c is used to put the 8042 into reset - do not se t any of the other bits in register 0x2c, as this may produce undesired results. it is not necessary to reset the 8042 if the isolation bi ts are used for a sleep state where vcc does not go inactive (s1, s2). note: it not necessary to reset the 8042 when iso_mode bit is set to ?0?, and m_iso and k_iso isolation bit are not set. this is because nlpcpd goes inactive high (it will remove isolation of the signals when system sleep state is exited) pr ior to npci_reset going inactive high. the npci_reset goi ng inactive high resets the 8042. user note regarding external keyboard and mouse: this is an application matter resulting from the be havior of the external 8042 in the keyboard. when the external keyboard and external mouse ar e powered up, the kdat and mdat lines are driven low. this sets the kbd bit (d3) and the mouse bi t (d4) of the pme wake status register since the kdat and mdat signals cannot be isolated internal to the part. this causes an nio_pme to be generated if the keyboard and/or mouse pme events are enabled. note that the keyboard and mouse isolation modes only prevent the internal 8042 in the part from setting these status bits. case 1: keyboard and/or mouse powered by vtr the kbd and/or mouse status bits will be set u pon a vtr por if the ke yboard and/or mouse are powered by vtr. in this case, an nio_pme wi ll not be generated, since the keyboard and mouse pme enable bits are reset to zero on a vtr por. the bios software needs to clear these pme status bits after power-up. case 2: keyboard and/or mouse powered by vcc the kbd and/or mouse status bits will be set up on a vcc por if the keyb oard and/or mouse are powered by vcc. in this case, an nio_pme will be generated if the enable bits were set for wakeup, since the keyboard and mouse pme enable bits are vt r powered. therefore, if the keyboard and mouse are powered by vcc, the enable bits for keyboard an d mouse events should be cleared prior to entering a sleep state where vcc is removed (i.e., s3) to prevent a false pme from being generated. in this case, the keyboard and mouse should only be used as pme and/ or wake events from the s0 and/or s1 states. the bios software needs to clear these pme status bits after power-up. 7.27 general purpose i/o the lpc47m172 provides a set of flexible input/output control functions to the system designer through the 13 independently programmable g eneral purpose i/o pins (gpio). the gpio pins can perform basic
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 124 smsc lpc47m172 datasheet i/o and can be individually enabled to generate a pme (except gp24). gpios must be programmed as inputs to generate a pme. 7.27.1 gpio pins the table 7.16 summarizes the gpio functionality, incl uding pme, either edge triggered interrupt (eeti) input capability and the power source for the buffer on the i/o pads. table 7.16 - gpio summary default function alt func 1 alt func 2 pwr well pci reset vcc por vtr por pme/eeti ncdc_dwn _enab gp24 - vtr - - input - gp10 - - vtr - - input pme gp11 - - vtr - - input pme gp12 - - vtr - - input pme gp13 - - vtr - - input pme gp14 - - vtr - - input pme gp15 - - vtr - - input pme gp16 fan_tach1 (note 1) - vtr - - input pme gp17 fan_tach2 (note 1) - vtr - - input pme ddcsda_5v gp20 eeti0 vtr note 1 - - hi-z pme/eeti ddcscl_5v gp21 eeti1 vtr note 1 - - hi-z pme/eeti ddcsda_3v gp22 - vtr note 1 - - hi-z pme ddcscl_3v gp23 - vtr note 1 - - hi-z pme note 1: when ddc functions are selected, these pins r equire external pull-ups to appropriate voltages. 7.27.2 description each gpio port has a 1-bit data register and an 8-bit co nfiguration control register . the data register for each gpio port is represented as a bit in one of the 8- bit gpio data registers, gp1 to gp2. the bits in these registers reflect the value of th e associated gpio pin as follows. pin is an input: the bit is the value of the gpio pin. pin is an output: the value writte n to the bit goes to the gp io pin. latched on read and write. all of the gpio registers are located in the gpio/runtime register logical device (see gpio runtime registers section when ld_num=0 and chap ter 10 runtime register block runtime registers sections when ld_num=1). the gpio ports with thei r alternate functions and configuration state register addresses are listed in table 7.17.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 125 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 7.17 - general purpose i/o port assignments default function alt. func. 1 alt. func. 2 data register 1 data register bit no. gpio runtime register offset (hex) ncdc_dwn_enab gp24 - 0 gp10 - - 1 gp11 - - 2 gp12 - - 3 gp13 - - 4 gp14 - - 5 gp15 - - 6 gp16 fan_tach1 - gp1 7 15 gp17 fan_tach2 - 0 ddcsda_5v gp20 eeti0 1 ddcscl_5v gp21 eeti1 2 ddcsda_3v gp22 - 3 ddcscl_3v gp23 - 4 reserved - - gp2 7:5 16 note 1: the gpio data and configuration registers are loca ted in gpio/runtime regist er block at the offset shown from the gpio/runtime register block logical device base address. 7.27.3 gpio control each gpio port has an 8-bit control re gister that controls the behavior of the pin. these registers are defined in gpio runtime registers section when ld _num=0 and chapter 10 runtime register block runtime registers when ld_num=1. each gpio port may be configured as either an input or an output. if the pin is configured as an output, it can be programmed as open-drain or push-pull. inputs and outputs can be configur ed as non-inverting or inverting. bit[0] of each gpio conf iguration register determines the po rt direction, bit[1] determines the signal polarity, and bit[7] determines the output driver type select. the polarity bit (bit 1) of the gpio control registers control the gpio pin when the pin is configured for the gpio function and when the pin is configured for the alte rnate function for all pins, with the exception of the either edge triggered interrupts and ddc functions. the basic gpio configuration opti ons are summarized in table 7.18. table 7.18 - gpio configuration summary selected function direction bit polarity bit description b0 b1 0 0 pin is a non-inverted output. 0 1 pin is an inverted output. 1 0 pin is a non-inverted input. gpio 1 1 pin is an inverted input.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 126 smsc lpc47m172 datasheet 7.27.4 gpio operation the operation of the gpio ports is illustrated in figure 7.4. gpio pin gpio data register bit-n sd-bit gpx_nior gpio configuration register bit-1 (polarity) gpio configuration register bit-0 (input/output) 1 0 d-type transparen t gpx_niow dq qd figure 7.4 - gpio function illustration note: figure 7.4 is for illustration purposes only and is not intended to suggest specific implementation details. when a gpio port is programmed as an input, reading it through the gpio data regi ster latches either the inverted or non-inverted logic value present at the gp io pin. writing to a gpio port that is programmed as an input has no effect (table 7.19) when a gpio port is programmed as an output, the lo gic value or the inverted logic value that has been written into the gpio data register is output to the gpio pin. reading fr om a gpio port that is programmed as an output returns the last value written to the data register (table 7.19). when the gpio is programmed as an output, the pin is excluded from the pme logic. table 7.19 - gpio read/write behavior host operation gpio input port gpio output port read latched value of gpio pin last write to gpio data register write no effect bit placed in gpio data register
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 127 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 7.27.5 gpio pme functionality the lpc47m172 provides 12 gpios t hat can directly generate a pme. see the table 7.16. the polarity bit in the gpio control registers select the edge on thes e gpio pins that will set the associated status bit in the pme_sts2 and pme_sts3 regist ers. the default is the low-to -high edge. if the corresponding enable bit in the pme_en2 and pme_en3 registers and the pme_en bit in the pme_en register is set, a pme will be generated. the pme registers are runt ime registers which are located at the address contained in the configuration regi sters 0x60 and 0x61 in power control/runtime register block logical device. see gpio runtime registers section when ld_num=0 and chapter 10 runtime register block runtime registers when ld_num=1.the pme status bits for the gpios are cleared on a write of ?1?. the following gpios are dedicated wakeup gpios with a status and enable bit in the pme status and enable registers: gp10-gp17 gp20-gp23 the following pme status and enabl e registers for these gpios: pme_sts2 and pme_en2 for gp10-gp17 pme_sts3 and pme_en3 for gp20-gp23 7.27.6 either edge triggered interrupts gp21 and gp22 are implemented such that they allow an pme interrupt to be generated on both a high- to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. the either edge triggered interrupts (eeti) function as follows: if the eeti f unction is selected for the gpio pin, then the bits that cont rol input/output, polarity and open drain/push-pull have no effect on the function of the pin. however, the polarity bit does affe ct the value of the gp bit (i.e., register gp2, bit 2 for gp22). a pme interrupt occurs if the pme enable bit is set for the corresponding gpio and the eeti function is selected on the gpio. the pme status bit is set wh en the eeti pin transitions (on either edge) and are cleared on a write of ?1?. there are also status bits for the eetis loca ted in the msc_sts register, which are also cleared on a write of ?1?. the msc_sts regist er provides the status of all of the eeti interrupts within one register. the pme or msc status is valid whether or not the interrupt is enabled and whether or not the eeti function is selected for the pin. the msc_sts register is defined in gpio runtime registers section when ld_num=0 and chapter 10 runtime register block runtime registers when ld_num=1. 7.28 pme support the lpc47m172 offers support for power management events (pmes), also referred to as a system control interrupt (sci) events in an acpi system. a power management event is indicated to the chipset via the assertion of the nio_pme signal. in th e lpc47m172, the nio_pme is asserted by active transitions on the ring indicator inputs nri1 and nri2 , active keyboard-data edges, active mouse-data edges, programmable edges on gpio pins and fan tachometer event. the nio_pme pin, can be programmed to be active high or active low via the pola rity bit in the nio_pme register. the output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the nio_pme register. the nio_pme pin function defaults to active low, open-dr ain output. the nio_pme register is located at an offset 0x16 from power control/ru ntime register block logical devi ce base address. see chapter 8 power control runtime registers and chapter 10 runtime register block runtime registers.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 128 smsc lpc47m172 datasheet the pme functionality is controlled by the pme status and enable regist ers in the power control/runtime register block, which is located at the address pr ogrammed in configuration registers 0x60 and 0x61 in power control/runtime register logical device. the power control logical device is selected when ld_num=0, and the runtime registers local device is selected when ld_num=1. the pme enable bit, pme_en, globally controls pme wake-up events. w hen pme_en is inactive, the nio_pme signal can not be asserted. when pme_en is asserted, any wa ke source whose individual pme wake enable register bit is asserted can caus e nio_pme to become asserted. the pme status register indicates that an enabled wa ke source has occurred, and if the pme_en bit is set, asserted the nio_pme signal. the pme status bit is asserted by active transitions of pme wake sources. pme_status will become asserted indepe ndent of the state of the global pme enable bit, pme_en. the following pertains to the pme status bits for each event: ? the output of the status bit for each event is co mbined with the corresponding enable bit to set the pme status bit. ? the status bit for any pending events must be cleared in order to clear the pme_sts bit. status bits are cleared on a write of ?1?. for the gpio events, the pol arity of the edge used to set the status bit and generate a pme is controlled by the polarity bit of the gpio control register. fo r non-inverted polarity (default) the status bit is set on the low-to-high edge. if the eeti function is selected for a gpio then both a high-to-low and a low-to-high edge will set the corresponding pme status bits. status bits are clea red on a write of ?1?. the pme wake registers also include status and en able bits for the fan tachometer input. the fan tachometers are not intended to be wakeup events and are only valid when vcc power is active. user note: clear the pme enable bits for the fan tachometers before removing vcc. see the ?keyboard and mouse pme generation? sect ion for information about using the keyboard and mouse signals to generate a pme. in the lpc47m172 the nio_pme pin can be programmed to be an open drain, active low, driver. the lpc47m172 nio_pme pin is fully isolated from other ex ternal devices that might pull the nio_pme signal low; i.e., the nio_pme signal is capable of being dr iven high externally by another active device or pullup even when the lpc47m172 vcc is grounded, providin g vtr power is active. the lpc47m172 nio_pme driver sinks 6ma at .55v max (see section 4.2.1.1 dc s pecifications, page 122, in the ?pci local bus specification,? revision 2.1). 7.28.1 ?wake on specific key? option the lpc47m172 has logic to detect a single keyboard scan code for wakeup (pme generation). the scan code is programmed onto the keyboard scan code regist er, a runtime register at offset 0x11 from the base address located in the primary base i/o address in power control/runtime register block logical device. this register is powered by vtr and reset on vtr por. the pme status bit for this event is located in the pme_sts1 register at bit 5 and the pme enable bit for this event is located in the pme_en1 register at bit 5. see chapter 8 power co ntrol runtime registers or chapter 10 runtime register block runtime regi sters for a definition of these registers. data transmissions from the keyboard consist of an 11-bit serial data stream. a logic 1 is sent at an active high level. the following table shows the functions of the bits. bit function 1 start bit (always 0) 2 data bit 0 (least significant bit) 3 data bit 1
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 129 smsc/non-smsc register sets ( rev. 01-11-07) datasheet bit function 4 data bit 2 5 data bit 3 6 data bit 4 7 data bit 5 8 data bit 6 9 data bit 7 (most significant bit) 10 parity bit (odd parity) 11 stop bit (always 1) the timing for the keyboard clock and data signals are shown in the ?timing diagrams? section. the process to find a match for the scan code stored in the keyboard scan code register is as follows: begin sampling the data at the first falling edge of the keyboard clock following a period where the clock line has been high for 115-145usec. the data at this fi rst clock edge is the start bit. the first data bit follows the start bit (clock 2). sample the data on eac h falling edge of the clock. store the eight bits following the stop bit to compare with the scan code st ored in the keyboard scan code register. sample the comparator within 100usec of the falling edge of clock 9 (for example, at clock 10). sample the parity bit and check that the 8 data bits plus the parity bit always have an odd number of 1?s (odd parity) . repeat until a match is found. if the 8 data bits match the scan code stored in the keyboard scan code register and the parity is correct, then it is considered a match. when a match is found and if the stop bit is 1, set the event status bit (bit 5 of the pme_sts1 register) to ?1? within 100usec of the falling edge of clock 10. the state machine will reset after 11 clocks and the process will restart. the process will continue until it is shut off by setting the spekey_en bit (see following sub-section). the state machine will reset if there is a period where the clock remains high for more than one keyboard clock period (115-145usec) in the middle of the transmi ssion (i.e., before clock 11). this is to prevent the generation of a false pme. the spekey_en bit at bit 1 of the cl ocki32 register at 0xf0 in power control/ru ntime register block logical device is used to control the ?wake-on-specific fe ature. this bit is used to turn the logic for this feature on and off. it will disable the 32khz clock inpu t to the logic. the logic will draw no power when disabled. the bit is defined as follows: 0= ?wake on specific key? logic is on (default) 1= ?wake on specific key? logic is off note: the generation of a pme for this ev ent is controlled by the pme enab le bit (located in the pme_en1 register at bit 5) when the logic for feature is turned on. 7.29 fan monitoring the chip monitors the speed of the fans by utilizing fan tac hometer input signals from fans equipped with tachometer outputs. the fan tachom eter inputs are monitored by usin g the fan tachomet er registers. these signals, as well as the fan tac hometer registers, are described below.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 130 smsc lpc47m172 datasheet 7.29.1 fan tachometer inputs a fan tachometer input is used to measure the speed at which a fan is rotating. the fan tachometer input is a train of square pulses with a 50% duty cycle (see fi gure 7.5) that are derived from the magnetic fields generated by the rotating rotor of the fan. the s peed of the fan can be deter mined by calculating the period of the fan tac hometer input pulse. note: all calculations are based on fans that emit 2 square pulses per revo lution. reading registers reflect a count value for one complete revolution (2 pulses). the clock source to the fan tachometer logic is 90khz (nominal) derived from 14.318 mhz clock and is active when vcc power is active. fan tachometer input clock source for counter t p t r = revolution time = 60/rpm (sec) t p = pulse time = t r /2 (two pulses per revolution) f = 90khz (nominal) t r figure 7.5 - fan tachometer input and clock source the counter is used to deter mine the period of the fan tachometer i nput pulse. this counter is reset on the rising edge of every other fan tach ometer input pulse, and thus meas ures the number of clock pulses generated by the clock source for the duration of one fan tachometer revolution. since two fan tachometer input pulses are generated per revolution of the fan rotor, the speed of the fan is easily calculated. the fan tachometer input resets the counter on every other pulse and simultaneously loads the count into its respective reading register. this value is used by t he operating system to monitor the speed of the fan. the fan tachometer reading regist ers contain the number of 11.11us periods (90khz nominal) between full fan revolutions. fans produce 2 pulses per revolu tion. these registers are upd ated at least once every second. this register is latched on the rising ed ge of every other fan tachom eter pulse and when the fan count reaches ffffh. the value ffffh indicates that the fan is not spinning (s talled fan event), or the tachometer input is not connected to a valid sign al (this could be triggered by a counter overflow) the fan tachometer reading registers always retu rn an accurate fan tachometer measurement, even when a fan is disabled or non-functional. the tachometer reading registers ar e 16 bits, unsigned. when one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. the order is lsb first, msb second. these registers are read onl y ? a write to these registers has no effect. the fan tachometer reading regi sters are tach1 lsb, tach1_msb, tach2 lsb and tach2 msb. see chapter 8 power control runtime registers and chapte r 10 runtime register block runtime registers. 7.29.2 detection of a stalled fan the fan failure bit in the interrupt status register is set in the even t of a stalled fan. note: the fan tachometer reading register , which holds the count value, does not roll over ? it stays at ffffh in the
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 131 smsc/non-smsc register sets ( rev. 01-11-07) datasheet event of a stalled fan. the intern al count register does rollover, however, and continuously counts to ffffh as long as the fan is stalled. in the event the counter reaches ffffh, the pme status bit is set and the count value is latched into the register. the second subsequent fan tach pulse re sets the counter but does not latch the count value. every second fan tach pulse latches the fan count value into the fan tachometer register except for this special case. the fan stalled event can generate a pme if properly enabled. note the fan stalled pme is not a wakeup event, and it can indicate a fan stalled event if vcc is active. 7.30 hard drive and power led logic 7.30.1 hard drive front panel led (red) table 7.20 - hard drive front panel pins name buffer power well description nscsi ispu_400 vcc scsi drive active input nhd_led od12 vcc hard drive front panel led open-drain output nsecondary_hd ispu_400 vcc ide secondary drive active input nprimary_hd ispu_400 vcc ide primary drive active input notes: ? the nhd_led requires external pull-up to vcc. ? ispu_400 is defined as: input with schmitt trigger, 400 mv hysteresis, with 30ua internal pull-up. ? the nhd_led pin is a logical and of the inputs np rimary_hd, nsecondary_hd and nscsi used to drive a single color led. the inputs are internally pulled to vcc. see table belo w for state definitions. ? the nhd_led pin is used at the system?s front panel hea der to drive the hard drive activity led. note that external leds should be driven such that the volt age at the nhd_led pin does not exceed 5v. the output is open-drain and should be externally pulled to vcc through a resistor. table 7.21 - nhd_led truth table inputs output nprimary_hd nsecondary_hd nscsi nhd_led notes 0 x x 0 led on x 0 x 0 led on x x 0 0 led on 1 1 1 hi-z led off
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 132 smsc lpc47m172 datasheet smsc i/o red vcc nhd_led 220 ohms figure 7.6 - nhd_led circuit 7.30.2 yellow and green power led pins table 7.22 - led pins name buffer power well description grn_led od24 vtr green power led open-drain output ylw_led od24 vtr yellow power led open-drain output nslp_s5 i vtr input from south bridge for transitioning to the s5 power state note: the leds require external pull-up to vtr. the green and yellow led outputs are controlled by the led register accessible via the lpc bus. the grn_ylw bit controls which output is asserted. in addition, the sdy_blk bit indicates whether the selected led is steady or blinking. the led regist er is defined in chapter 10 runtime register block runtime registers. these led outputs are also controlled by the nslp_s5 sl eep input pin. the functi onality is shown in the table below. the green and yellow led outputs are powered by vtr. table 7.23 - led truth table inputs outputs nslp_s5 grn_ylw bit sdy_blk bit grn_led ylw_led 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0.67 hz 1 0 1 0 hi-z
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 133 smsc/non-smsc register sets ( rev. 01-11-07) datasheet inputs outputs nslp_s5 grn_ylw bit sdy_blk bit grn_led ylw_led 1 1 0 0.67 hz 0 1 1 1 hi-z*** 0 notes: ? *** default state ? the led is on in the hi-z state. the led is blinki ng at 0.67 hz in the 0.67 hz state. the 32.768 khz clock input is used to control the blink rate and duty cycle of the leds. the blink rate is 0.67hz, and the duty cycle is 39.6%. this corresp onds to a led low output of exactly 0.90625 seconds (depending on the accuracy of the 32.768 khz clock). ylw_led and grn_led require external pull-ups to power the leds. a value of 220ohms to vtr is recommended. these are open drain active high outputs. when the leds are off, the open drain output is sinking the current from vtr through the 220ohm resistor to ground. when the leds are on, they are powered through the 220ohm resistor. the following figure shows the recommended external led circuit. smsc i/o green yellow vtr grn_led ylw_led 220 ohms 220 ohms figure 7.7 - ylw_led/grn_led circuit 7.31 power generation (5v) 7.31.1 reference pins table 7.24 - reference generation pins name buffer max out current power well description ref5v ao 3.3ma vcc 5v reference output ref5v_stby ao 3.3ma vtr highest system standby voltage o an : analog output, 5v level. see dc characteristics see the ?elect rical characteristics? section.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 134 smsc lpc47m172 datasheet 7.31.2 5v main reference generation ref5v is used to help power-up various system components? 5v tolerant buffers. this signal is used to guarantee there are no power sequencing requirem ents at each particular system component. ref5v is powered by vcc when vcc5v < vcc. upon motherboard power-up, ref5v is an analog output signal that tracks either vcc or vcc5v (through an external pull-up resistor), whichever is greater in amplitude. ref5v becomes a high impedance input while tracking the vcc power supply. table 7.25 - ref5v main supply ref5v vcc5v < vcc vcc vcc5v > vcc hi-z ref5v 1k vcc5v backdrive protection vcc (3.3v) smsc i/o figure 7.8 - ref5v circuit note: the maximum voltage drop across the diode is 350mv. 7.31.3 5v standby reference generation ref5v_stby is generated in the same manner as ref5v, but in reference to v_5p0_stby and vtr instead. ref5v_stby serves the same purpose as ref5v, but tracks different power supplies. ref5v_stby is an analog ou tput signal that tracks ei ther vtr or v_5p0_stby, whichever is greater in amplitude. upon motherboard power-up, ref5v_stby is an an alog output signal that tracks either vtr or v_5p0_stby (through an external pull-up resistor), whichever is greater in amplitude. ref5v_stby becomes a high impedance input while tracking the v_5p0_stby power supply. ref5v_stby is powered by vtr when vtr > v_5p0_stby. table 7.26 - ref5v_stby standby supply ref5v_stby v_5p0_stby < vtr vtr v_5p0_stby > vtr hi-z
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 135 smsc/non-smsc register sets ( rev. 01-11-07) datasheet r e f 5 v _ s t b y 1k v_5p0_stby v t r ( 3 . 3 v ) backdrive protection smsc i/o figure 7.9 - ref5v_stby note: the maximum voltage drop across the diode is 350mv. 7.31.4 reference timings see figure 13.25 to figure 13.28 in the ?timing diagrams? section. 7.32 ide reset output pin nide_rst is an open drain buffered copy of npci_r eset. this signal requires an external 1kohm pull-up to vcc5v. this signal will be low when vcc5v=0 since it is externally pulled up to vcc5v. table 7.27 - nide_rstdrv pin name buffer power well description nide_rstdrv od8 vcc ide reset output table 7.28 - nide_rstdrv truth table npci_reset (input) nide_rstdrv (output) 0 0 1 hi-z see table 13.1 for nide_rstdrv timing. 7.33 pci reset output pins the npcirst_out is 3.3v buffered copy of npci_r eset. the npcirst_out2 is 3.3v buffered copy of npci_reset. the npcirst_out and npcirst_out2 signals will be low when vcc=0.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 136 smsc lpc47m172 datasheet table 7.29 - npcirst_out pins name buffer power well description npcirst_out op14 vtr buffered pci reset output npcirst_out2 op14 vtr buffered pci reset output table 7.30 - npcirst_out and npcirst_out2 truth table input outputs npci_reset npcirst_out npcirst_out2 0 0 0 1 1 1 see table 13.2 for npci_rstout and npci_rstout2 timings. 7.34 voltage translation circuit table 7.31 - voltage translation ddc pins name buffer power well description ddcsda_5v/ gp20 io_sw vtr 5v ddc data iod/ gpio (note) ddcscl_5v/ gp21 io_sw vtr 5v ddc clock iod/ gpio (note ) ddcsda_3v/ gp22 io_sw vtr 3.3v ddc data iod/ gpio (note) ddcscl_3v/ gp23 io_sw vtr 3.3v ddc clock iod/ gpio (note) note: the ddc_5v signals require external pull-up to vcc5v. the ddc_3v signals require external pull-up to vcc. if ddc functions are selected on the pins, the pins will tri-state when vcc is removed. the vga ddc voltage translation circuitry is used in co njunction with integrated vga chipsets. since the chipset operates at 3.3v signal levels and the vg a signals are specified at 5v signal levels, on-board voltage translation is needed for the ddc signals. this is a non-inverting translation. see the table 7.32 and table 7.33 for further details on the logic. the ddc data pins and the ddc clock pins function as inputs shorted together through the isolation resistor. the ddc signals require external pull-up re sistors on lpc47m172. see the ?pins that require external resistors? section for resistor va lues. see figure 7.10 for recommended schematic implementation. note the switch is always on afte r the ddc functions are select ed on the gpio pins. that is, the switch is controlled by t he gpio alternate function select bits. once the ddc functions are selected, the switch is closed and remains closed when vc c is removed. the current flow is controlled by the external signals on the ddc pins. see the tables below for the current flow across the switch based on the voltage levels on the pins. the switch provides a 25ohm resistance to ground. this circuit requires esd protection external to the ch ip to protect the device from hot-plugging on the vga connector. see the ?electrical characteristics? section for current and voltage requirements. due to the multiplexing with gpio pins, these pins are powered by vtr. (without the multiplexing requirement, these pins could be powered by vcc).
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 137 smsc/non-smsc register sets ( rev. 01-11-07) datasheet note: if any of the alternate function select bits in gp20 to gp23 registers are set for ddc function, the ddc functions will be selected on all four gp20 to gp 23 pins. however, it is recommended that the ddc functions be selected via the alternate function select bits in all of the gp20 to gp23 registers when using the ddc functions. the gp20 to gp23 registers are def ined in chapter 8 power control runtime registers and chapter 10 runtime register block runtime registers. table 7.32 - vga ddcsda voltage translation logic ddc vs. gpio alternate function select bit/s ddcsda_3v ddcsda_5v current across the switch gpio/eeti/reserved don?t care don? t care no current flow (0 ma) ddc (default) 0v 0v current flows from ddcsda_5v or ddcsda_3v ddc (default) 3.6v (max) 5.5v (max) no current flow (0 ma) table 7.33 - vga ddcscl voltage translation logic ddc vs. gpio alternate function select bit/s ddcscl_3v ddcscl_5v current across the switch gpio/eeti/reserved don?t care don? t care no current flow (0 ma) ddc (default) 0v 0v current flows from ddcscl_5v or ddcscl_3v ddc (default) 3.6v (max) 5.5v (max) no current flow (0 ma)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 138 smsc lpc47m172 datasheet ddcscl_3v ddcsda_3v vcc 4.7k 4.7k mch ddcsda_5v ddcscl_5v vga connector vcc5v 2.2k 2.2k 6.2v 6.2v lpc47m172 see note note: the switch is implemented as an n-channel sw itch that will not pass a full voltage swing. it provides a current path to ground. the board designer should treat each signal pair to the switch as a separate bus with a resistance in the path. the maximum resistance of the switch between any bus to any other bus is 25ohms (when the switch is on). when the switch is off t he impedance is hi-z and the current is zero. the design requires pull-ups on each of the busses shown above. it is recommended that the pullups be selected so that the total maximum current on both busses does not exceed 2ma to limit the voltage drop across the switch. en gpio alternate function select bit 25ohm max 25ohm max figure 7.10 - vga ddc voltage translation circuit 7.35 smbus isolation circuitry table 7.34 - smbus isolation pins name buffer power well description smb_clk_m io_sw vtr main well smbus clock smb_dat_m io_sw vtr main well smbus data smb_clk_r io_sw vtr resume well smbus clock smb_dat_r io_sw vtr resume well smbus data the smbus isolation circuitry is used to isolate the main smbus signals from the resume smbus signals during power down modes. the smb data pins and the smb clock pins function as inputs shorted together through the isolation resistor when the switch is closed. the smbus signals require external pull-up resistors on lpc47m172. see figure 7.11 for reco mmended schematic implement ation. the switch is controlled by the pwrgd_ps signal. the switch is clos ed as long as pwrgd_ps is ?1?. the current flow is controlled by the external signals on the smb pins. see table 7.35 and table 7.36 for the current flow across the switch based on the voltage levels on th e pins. the switch provides a 25ohm resistance to ground. these pins are powered by vtr.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 139 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 7.35 - smb_clk isolation logic pwrgd_ps smb_clk_m smb_clk_ r current across the switch 0 don?t care don?t care no current flow (0 ma) 1 0v 0v current flows from smb_clk_r or smb_clk_m 1 3.6v (max) 3.6v (max) no current flow (0 ma) table 7.36 - smb_dat isolation logic pwrgd_ps smb_dat_m smb_dat_r current direction across the switch 0 don?t care don?t care no current flow (0 ma) 1 0v 0v current flows from smb_dat_r or smb_dat_m 1 3.6v (max) 3.6v (max) no current flow (0 ma) smb_dat_m smb_clk_m vcc 2.7k 2.7k ich, cnr, dimms, clk gen smb_clk_r smb_dat_r ich, pci vtr 2.7k 2.7k lpc47m172 see note pwrgd_ps en note: the switch is implemented as an n-channel switch that will not pass a full voltage swing. it provides a current path to ground. the board designer should treat each signal pair to the switch as a separate bus with a resistance in the path. the maximum resistance of the switch between any bus to any other bus is 25ohms (when the switch is on). when the switch is off the impedance is hi-z and the current is zero. the design requires pull-ups on each of the busses shown above. it is recommended that the pullups be selected so that the total maximum current on both busses does not exceed 2ma to limit the voltage drop across the switch. 25ohm max 25ohm max figure 7.11 - smbus isolation circuit
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 140 smsc lpc47m172 datasheet 7.36 ps_on logic table 7.37 - nps_on, ncpu_p resent and nslp_s3 pins name buffer power well description nps_on od8 vtr power supply turn-on open drain output ncpu_present ispu_400 vtr cpu present input from processor nslp_s3 i vtr s3 power state input from south bridge the nps_on is a function of nslp_s3 and ncpu _present according to the truth table below. the ncpu_present is the signal from the processor that tells the system whether or not a processor has been plugged in. the ncpu_present will be pulled to vtr through a 30ua resistor inside the chip. the nps_on is used as the power down signal for the power supply. since nps_on is an open drain output, it may need to be pulled through a 1kohm resistor to v_5p0_stby external to the chip if such a pull-up is not provided on the power supply. the power supply turn-on circuit behaves according to the table below. table 7.38 - nps_on truth table inputs output ncpu_present nslp_s3 nps_on 0 0 hi-z 0 1 0 1 0 hi-z 1 1 hi-z see table 13.3 for nps_on timing. 7.37 pwrgd_3v logic table 7.39 - pwrgd_3v, nf prst and pwrgd_ps pins name buffer power well description nfprst ispu_400 vtr reset input from front panel pwrgd_ps ispu_400 vtr power good input from power supply pwrgd_3v o8 vtr power good output the pwrgd_3v is an and function of pwrgd_ps and nfprst. the inputs, pwrgd_ps and nfprst have hysteresis a nd are internally pulled to vtr through a 30ua resistor. the nfprst is debounced internally. nfprst has internal debounce circuitry that is valid on both edges for at least 16ms before the output is changed. the 32.768khz is used to meet the ti ming requirement. see figure 7.14 for nfprst debounce timing.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 141 smsc/non-smsc register sets ( rev. 01-11-07) datasheet note: the actual minimum debounce time is 15.8msec see table 13.5 for pwrgd_3v timing. table 7.40 - pwrgd_3v truth table inputs output nfprst pwrgd_ps pwrgd_3v 0 0 0 0 1 0 1 0 0 1 1 1 the following figure shows the discrete implementation for the creation of the pwrgd_3v signal on the motherboard. pwrgd_ps pwrgd_3v nfprst 3.3kohm 1uf figure 7.12 - pwrgd_3v circuit, discrete implementation (showing nfprst input debounce circuitry) the following figure represents the integr ation of the logic into the lpc47m172. smsc i/o pwrgd_ps pwrgd_3v n f p r s t debounce circuitry figure 7.13 - pwrgd_3v circuit in lpc47m172
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 142 smsc lpc47m172 datasheet nfprst (before debounce) press release 15.8msec min 15.8msec min the next nfprst press will be detected starting here internal nfprst (after debounce) figure 7.14 - nfprst timing 7.38 sck_bjt_gate output table 7.41 - sck_bjt_gate pin name buffer power well description sck_bjt_gate od8 vtr open-drain gate output for the sck_bjt_gate in s3 note: the sck_bjt_gate requires external pull-up to v_5p0_stby. the sck_bjt_gate pin is an open drain output that provides the gate signal for sck_bjt in the s3 power state. this circuit is used for glitch protection on the sck line when moving in to and out of the s3 power state. this signal is only required for des igns utilizing rambus memory. this output functions according to the table below. see the figure below for the circuit implementation. table 7.42 - sck_bjt_gate truth table pwrgd_3v (input) sck_bjt_gate (output) 0 hi-z 1 0
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 143 smsc/non-smsc register sets ( rev. 01-11-07) datasheet smsc i/o sck_bjt_gate v_5p0_stby 1k mch rmb_sck figure 7.15 - sck_bjt_gate circuit see table 13.4 for sck_bjt_gate timing. 7.39 backfeed cut and latch ed backfeed cut circuitry table 7.43 - nbackfeed_cut and latched_bf_cut pins name buffer power well description nbackfeed_cut od8 vtr open-drain output used for str circuitry latched_bf_cut op14 vtr latched backfeed cut output for str circuitry note: the nbackfeed_cut requires an external pull-up to v_5p0_stby. nbackfeed_cut is a signal required by the s3 power state circuitry and is powered by the vtr supply. it is a function pwrgd_ps and nslp_s3 according to the table below. nbackfeed_cut is used to switch between the main voltage regulator and the suspend voltage regulator for various sub-systems when the system is transitioning into the s3 power state. table 7.44 - nbackfeed_cut truth table inputs output pwrgd_ps nslp_s3 nbackfeed_cut 0 0 hi-z 0 1 hi-z 1 0 hi-z 1 1 0
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 144 smsc lpc47m172 datasheet smsc i/o pwrgd_ps nslp_s3 n b a c k f e e d _ c u t backfeed_cut +5vtr +12 nslp_s5 l a t c h e d _ b f _ c u t 1k 470 ohms 1k 1k 1k 470 ohms +12 +5vtr figure 7.16 - backfeed cut and latched backfeed cut circuit the latched_bf_cut is generated from nbackfeed _cut and nslp_s5. it is powered by vtr. table 7.45 - latched_bf_cut truth table inputs output nbackfeed_cut (internal signal) nslp_s5 latched_bf_cut 0 0 0 0 1 0 1 0 0 0 to 1 (rising edge) 1 1 ?1? and no rising edge 1 no change (note) note: this is the condition when nbackfeed_cut stays hi gh and nslp_s5 goes low and then high again (see figure 7.19). application note: the figure below shows the power up sequence. the nbackfeed_cut signal follows the power rail up to its final value. the latched_bf_cut signal stays low and never turns on. the nslp_s5 goes to its high value when the power rails have stabilized, approximately 25msec after power on. nbackeed_cut is pulled low a period t1 after nslp_s5 goes high. the period t1 can be as short as 1msec. typical measured values are
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 145 smsc/non-smsc register sets ( rev. 01-11-07) datasheet approximately 200msec. the t1 and t2 values are guarant eed by the inherent design of the system and are not controlled by the lpc47m172. t1 t2 v_5p0_stby nslp_s3 pwrgd_ps nbackfeed_cut nslp_s5 latched_bf_cut figure 7.17 - latched backfeed cut power up sequence table 7.46 - latched backfeed cut power up sequence timing name description min typ max units t1 nslp_s5 inactive to nbackfeed_cut active 1 200 msec t2 nslp_s5 inactive after power rails have stabilized 25 msec note: periods t1 and t2 should be guaranteed by the inher ent design of the system. these timings are not controlled by the lpc47m172. there are two possible timing sequences following the power up signal sequencing. the first possible sequence is with nslp_s5 staying high and nbackfeed_cut transitioning from low to high, remaining high for an undetermined period and then going back to low. at this point, the system returns to the end of the power-up sequence. during these nbackfeed_cut transitions, the propagation delays, rise and fall times for latched_bf_cut are as described in the figure belo w. the first sequence can start at the end of the power-up sequence at any time. nslp_s3 pwrgd_ps nslp_s5 nbackfeed_cut latched_bf_cut tpropr tr tf tpropf nslp_s5 = 1 figure 7.18 - latched backfeed cut sequence 1
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 146 smsc lpc47m172 datasheet the second possible sequence, shown in the figure below, is a normal powerdown sequence. the nbackfeed_cut signal goes from low to high wh en nslp_s3 goes low, and nslp_s5 goes from high to low 30usec to 65usec (t3) later. the latched_bf_cut signal goes high when nbackfeed_cut goes high and then latched_bf_cut returns to low when nslp_s5 goes low. the nbackfeed_cut stays high and nslp_s5 stays low for an indeterminate time and then nslp_s5 will go high. a minimum of 1msec (t4) later, nbackf eed_cut will go low and the system returns to the end of the power-up sequence when nslp_s3 and pwrgd_3v goes high. typical measured values of t4 are approximately 250msec. du ring all transitions, the propagation delays, rise and fall times and power regulation times for latched_bf_cut are as described in figure 7.19. the first sequence can start at the end of this power-up sequence at any time. tr tpropf tf tpropr t4 t3 nslp_s3 pwrgd_ps nbackfeed_cut nslp_s5 latched_bf_cut figure 7.19 - latched backfeed cut sequence 2 table 7.47 - latched backfeed cut sequence 1 and 2 timing name description min typ max units tr latched_bf_cut rise time. measured from 10% to 90%. 1 us tf latched_bf_cut fall time. measured from 90% to 10%. 1 us tpropf latched_bf_cut high to low propagation delay. measured from nbackfeed_cut/nslp_s5 threshold to 90% of latched_bf_cut 50 ns tpropr latched_bf_cut low to high propagation delay. measured from nbackfeed_cut/nslp_s5 threshold to 10% of latched_bf_cut 50 ns co output capacitance 25 pf cl load capacitance 50 pf t3 nbackfeed_cut inactive to nslp_s5 active 30 60 us t4 nslp_s5 inactive to nbackfeed_cut active 1 250 ms
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 147 smsc/non-smsc register sets ( rev. 01-11-07) datasheet the following figure shows a flowchart of the logic. start of suspend power up sequence nbackfeed_cut = 0 nslp_s5 = 0 latched_bf_cut = 0 nbackfeed_cut = 1? power rails stabilized? (period t2) (verified by ich) nslp_s5 = 1 (controlled by ich) nbackfeed_cut = 0? (period t1) end of power up sequence no yes yes no yes no nbackfeed_cut = 1? yes no latched_bf_cut = 1 (after tpropr) nslp_s5 = 0? latched_bf_cut = 0 (after tpropf) (this is end of t3) nslp_s5 = 1? period t4 nbackfeed_cut = 0 (controlled by nslp_s3 and pwrgd_ps) nbackfeed_cut = 0? latched_bf_cut = 0 (after tpropf) yes no no yes no yes main power active figure 7.20 - latched backfeed cut flowchart
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 148 smsc lpc47m172 datasheet 7.40 resume reset logic table 7.48 - nrsmrst pin name buffer power well description nrsmrst o8 vtr resume reset output v_5p0_stby pwr 5v standby the nrsmrst signal is the reset output for the ich re sume well. this signal is used as a power on reset signal as well as a brown-out sensor for the ich. the rising edge of nrsmrst is a delayed 3.3v buffered copy of v_5p0_stby. this delay, t reset_delay , nominally 32ms, starts when v_5p0_stby hits the trip point, v trip . note the nrsmrst will be inactive high after the t reset_delay only if vtr (3.3v) is present. otherwise, nrsmrst will be active low beyond the t reset_delay ? until vtr (3.3v) goes active. on the falling edge there is minimal delay, t reset_fall . note that v trip shown in figure 26 has a v trip_min and a v trip_max . see table below for timing and voltage parameters. note that no internal clock is available during nr smrst generation, so an internally generated delay is required. the requirements are loose enough that an onboard rc delay is permissible. this delay is only required at v_5p0_stby power on and brown-out recovery. see table 13.7 for nrsmrst timing. 7.41 cnr logic table 7.49 - cnr pins name type power well description naud_lnk_rst i vtr audio link reset input ncdc_dwn_enab/ gp24 io12 vtr codec down enable input/gpio ncdc_dwn_rst o12 vtr codec down reset output the cnr codec down enable circuitry is used in conjunction with soft audio and motherboards with a cnr slot. this feature allows the basic input / out put system (bios) to enable an audio cnr board. see figure and table below for implementation and definiti on of the input and output states. note that these signals are required in all sleep states. the cnr circuitry is powered from vtr. the ncdc_dwn_enab pin also functions as a gpio. this allows bios to drive the pin to a known state if the motherboard requires it. note that ncdc_ dwn_rst still follows the ncdc_dwn_enab pin even when it is functioning as a gpio output. the ncdc_dwn_enab/gp24 pin functions as follows: ? when the ncdc_dwn_enab function is selected on gp24 , it will be an input to the cnr logic. the polarity bit will not affect the input. ? if gp24 is programmed as gpio output the gp dat a bit will control ncdc_dwn_enab input to the cnr logic. the data bit will also be reflected on the gp24 pin as an output under both vcc and vtr power. the polarity bit will affect the output and in put to the cnr logic. the output type select bit will also affect the gp24 pin. ? if gp24 is programmed as gpio input, it will not affect the ncdc_dwn_enab input into the cnr logic. it will function as a normal gpio input and can be used as a pme event.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 149 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 7.50 - cnr logic truth table inputs output naud_lnk_rst ncdc_dwn_enab (note) ncdc_dwn_rst 0 0 0 0 1 0 1 0 1 1 1 0 note: if gp24 is programmed as gpio out put the gp data bit will also control ncdc_dwn_enab input to the cnr logic. this follows the boolean equation: (naud_lnk_rst)x( ncdc_dwn_enab )=ncdc_dwn_rst n c d c _ d w n _ e n a b naud_lnk_rst ncdc_dwn_rst 10k smsc i/o powered by vtr (3.3v) figure 7.21 - cnr circuit see table 13.6 for cnr timing.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 150 smsc lpc47m172 datasheet chapter 8 power control runtime registers table 8.1 shows the runtime registers summary in t he power control logical device. table 8.2 shows the runtime registers description in the power control l ogical device. these runtime registers can only be accessed when ld_num bit in the test 7 configurati on register is ?0? (see table 11.3). the register offsets are from the base address programm ed in the power control logical device. table 8.1 - power control runtime registers summary, ld_num bit = 0 register offset (hex) type pci reset vcc por vtr por soft reset register 00 r/w - - 0x00 - pme_sts 01 ? 03 r - - - - reserved ? reads return 0 04 r/w - - 0x00 - pme_en 05 ? 07 r - - - - reserved ? reads return 0 08 r/w - - 0x00 - pme_sts3 09 r/w - - 0x00 - pme_sts2 0a r/w - - 0x00 - pme_sts1 0b r - - - - reserved ? reads return 0 0c r/w - - 0x00 - pme_en3 0d r/w - - 0x00 - pme_en2 0e r/w - - 0x00 - pme_en1 0f r - - - - reserved ? reads return 0 10 r/w - - 0x03 - led 11 r/w - - 0x00 - keyboard scan code 12 r - - 0x00 - tach1 lsb 13 r - - 0x00 - tach1 msb 14 r - - 0x00 - tach2 lsb 15 r - - 0x00 - tach2 msb 16 r/w - - 0x80 - nio_pme register 17 r/w - - 0x00 - msc_sts 18 r/w 0x01 0x01 - - force disk change 19 r - - - - floppy data rate select shadow 1a r - - - - uart1 fifo control shadow 1b r/w 0xff 0xff - - interrupt generating register 1 1c r/w 0xff 0xff - - interrupt generating register 2 1d r - - - - uart2 fifo control shadow 1e-1f r - - - - reserved ? reads return 0
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 151 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 8.2 - power control runtime registers description, ld_num bit = 0 name reg offset (type) description pme_sts default = 0x00 on vtr por 0x00 (r/w) bit[0] pme_status = 0 (default) = 1 set when lpc47m172 would normally assert the nio_pme signal, independen t of the state of the pme_en bit. bit[7:1] reserved pme_status is not affected by vcc por, soft reset or hard reset. writing a ?1? to pme_status will clear it and cause the lpc47m172 to stop asserting nio_pme, in enabled. writing a ?0? to pme_status has no effect. n/a 0x01 ? 0x03 (r) bits[7:0] reserved ? reads return 0 pme_en default = 0x00 on vtr por 0x04 (r/w) bit[0] pme_en = 0 nio_pme signal assertion is disabled (default) = 1 enables lpc47m172 to assert nio_pme signal bit[7:1] reserved pme_en is not affected by vcc por, soft reset or hard reset n/a 0x05 ? 0x07 (r) bits[7:0] reserved ? reads return 0 pme_sts3 default = 0x00 on vtr por 0x08 (r/w) pme wake status register 3 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp20 bit[1] gp21 bit[2] gp22 bit[3] gp23 bits[7:4] reserved the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] will cl ear it. writing a ?0? to any bit in pme wake status register has no effect. pme_sts2 default = 0x00 on vtr por 0x09 (r/w) pme wake status register 2 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] will cl ear it. writing a ?0? to any bit in pme wake status register has no effect.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 152 smsc lpc47m172 datasheet name reg offset (type) description pme_sts1 default = 0x00 on vtr por 0x0a (r/w) pme wake status register 1 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] reserved (note 1) bit[1] ri2 bit[2] ri1 bit[3] kbd bit[4] mouse bit[5] spekey (wake on specific key) bit[6] fan_tach1 (note) bit[7] fan_tach2 (note) the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] will cl ear it. writing a ?0? to any bit in pme wake status register has no effect. note: ? when the gp1x/fan_tachx pin is configured as a gpio (gpio control regi ster bit 2 = 0), the associated pme status bit will never be set. ? when the pin is configured for the tachometer function (gpio control regi ster bit 2 = 1) and then the function is switched to the gpio function, the associated pme status bit will be cleared. n/a 0x0b (r) bits[7:0] reserved ? reads return 0 pme_en3 default = 0x00 on vtr por 0x0c (r/w) pme wake status register 3 this register is used to enable individual lpc47m172 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] gp20 bit[1] gp21 bit[2] gp22 bit[3] gp23 bits[7:4] reserved the pme wake enable register is not affected by vcc por, soft reset or hard reset.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 153 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description pme_en2 default = 0x00 on vtr por 0x0d (r/w) pme wake enable register 2 this register is used to enable individual lpc47m172 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if t he source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of t he wake source but will not assert the nio_pme signal. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake enable register is not affected by vcc por, soft reset or hard reset. pme_en1 default = 0x00 on vtr por 0x0e (r/w) pme wake enable register 1 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if t he source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of t he wake source but will not assert the nio_pme signal. bit[0] reserved (note 1) bit[1] ri2 bit[2] ri1 bit[3] kbd bit[4] mouse bit[5] spekey (wake on specific key) bit[6] fan_tach1 bit[7] fan_tach2 the pme wake enable register is not affected by vcc por, soft reset or hard reset. n/a 0x0f (r) bits[7:0] reserved ? reads return 0 led default = 0x03 on vtr por 0x10 (r/w) led register bit[0] grn_ylw 0 = select ylw_led if nslp_s5 if high 1 = select grn_led if nslp_s5 is high bit[1] sdy_blk 0 = blink at 0.67 hz with 39.6% duty cycle (0.59375 sec high, 0.90625 low) if nslp_s5 is high 1 = steady if nslp_s5 is high bit[7:2] reserved
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 154 smsc lpc47m172 datasheet name reg offset (type) description keyboard scan code default = 0x00 on vtr por 0x11 (r/w) keyboard scan code bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code tach1 lsb default = 0x00 on vtr por 0x12 (r) this register is least significant 8-bit of the 16-bit fan tachometer 1 reading. bit[0] fan_tach1 reading bit 0 ? bit[7] fan_tach1 reading bit 7 tach1 msb default = 0x00 on vtr por 0x13 (r) this register is most significant 8-bit of the 16-bit fan tachometer 1 reading. bit[0] fan_tach1 reading bit 8 ? bit[7] fan_tach1 reading bit 15 tach2 lsb default = 0x00 on vtr por 0x14 (r) this register is least significant 8-bit of the 16-bit fan tachometer 2 reading. bit[0] fan_tach2 reading bit 0 ? bit[7] fan_tach2 reading bit 7 tach2 msb default = 0x00 on vtr por 0x15 (r) this register is most significant 8-bit of the 16-bit fan tachometer 2 reading. bit[0] fan_tach2 reading bit 8 ? bit[7] fan_tach2 reading bit 15 nio_pme register default = 0x80 on vtr por 0x16 (r/w) bit[0] reserved bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain (default) 0=push pull msc_sts default = 0x00 on vtr por 0x17 (r/w) miscellaneous status register bits[1:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). bit[0] either edge triggered interrupt input 0 status. this bit is set when an edge occurs on the gp21 pin. bit[1] either edge triggered interrupt input 1 status. this bit is set when an edge occurs on the gp22 pin. bit[7:2] reserved. this bit always returns zero.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 155 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description force disk change default = 0x01 on vcc por 0x18 (r/w) force disk change bit[0] force disk change for fdc0 0=inactive 1=active bit[1] reserved force change 0 can be written to 1 but is not clearable by software. force change 0 is cleared on nstep and nds0 dskchg (fdc dir register, bit 7) = (nds0 and force change 0) or ndskchg setting the force disk change bit active ?1? forces the fdd ndskchg input active. bit[7:2] reserved floppy data rate select shadow 0x19 (r) floppy data rate select shadow bit[0] data rate select 0 bit[1] data rate select 1 bit[2] precomp 0 bit[3] precomp 1 bit[4] precomp 2 bit[5] reserved bit[6] power down bit[7] soft reset uart1 fifo control shadow 0x1a (r) uart fifo control shadow 1 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) int_gen1 default = 0xff on vcc por and hard reset 0x1b (r/w) interrupt generating register 1 (note 2) 0=corresponding interrupt frame driven low in the ser irq stream. this must be enabled through the int_g configuration register. bit[0] reserved bit[1] nint1 bit[2] nint2 bit[3] nint3 bit[4] nint4 bit[5] nint5 bit[6] nint6 bit[7] nint7 note: to enable/disable this register see logical device a (0xf1)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 156 smsc lpc47m172 datasheet name reg offset (type) description int_gen2 default = 0xff on vcc por and hard reset 0x1c (r/w) interrupt generating register 2 (note 2) 0=corresponding interrupt frame driven low in the ser irq stream. this must be enabled through the int_g configuration register. bit[0] nint8 bit[1] nint9 bit[2] nint10 bit[3] nint11 bit[4] nint12 bit[5] nint13 bit[6] nint14 bit[7] nint15 note: to enable/disable this register see logical device a (0xf1) uart2 fifo control shadow 0x1d (r) uart fifo control shadow 2 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) n/a 0x1e-0x1f (r) bits[7:0] reserved ? reads return 0 note 1: these bits are r/w bit, but have no effect on circuit operation. note 2: these bits when read indicate the current bit status. t hese bits are set to ?0? by writing ?0? to individual bit locations in this register. producing an interrupt in the ser_irq stream by setting these bits to ?0? overrides other interrupt sources for the ser_irq stream. no other functional logic in the lpc47m172 sets bits in the register. these bits are on ly cleared by writing ?1? to the bit location.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 157 smsc/non-smsc register sets ( rev. 01-11-07) datasheet chapter 9 gpio runtime registers table 9.1 shows the runtime registers summary in t he gpio logical device. table 9.2 shows the runtime registers description in the gpio logical device. these registers can only be accessed when ld_num bit in the test 7 configuration register is ?0? (see table 11.3). the register offset s are from the base address programmed in the gpio logical device. table 9.1 - gpio runtime registers summary, ld_num = 0 register offset (hex) type pci reset vcc por vtr por soft reset register 00 r/w - - 0x01 - gp10 01 r/w - - 0x01 - gp11 02 r/w - - 0x01 - gp12 03 r/w - - 0x01 - gp13 04 r/w - - 0x01 - gp14 05 r/w - - 0x01 - gp15 06 r/w - - 0x01 - gp16 07 r/w - - 0x01 - gp17 08 r/w - - 0x04 - gp20 09 r/w - - 0x04 - gp21 0a r/w - - 0x04 - gp22 0b r/w - - 0x04 - gp23 0c r/w - - 0x05 - gp24 0d-14 r - - - - reserved ? reads return 0 15 r/w - - 0x00 - gp1 16 r/w - - 0x00 - gp2 17-1f r - - - - reserved ? reads return 0
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 158 smsc lpc47m172 datasheet table 9.2 - gpio runtime registers description, ld_num = 0 name reg offset (type) description gp10 default = 0x01 on vtr por 0x00 (r/w) general purpose i/o bit 1.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp11 default = 0x01 on vtr por 0x01 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp12 default = 0x01 on vtr por 0x02 (r/w) general purpose i/o bit 1.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp13 default = 0x01 on vtr por 0x03 (r/w) general purpose i/o bit 1.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp14 default = 0x01 on vtr por 0x04 (r/w) general purpose i/o bit 1.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp15 default = 0x01 on vtr por 0x05 (r/w) general purpose i/o bit 1.5 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp16 default = 0x01 on vtr por 0x06 (r/w) general purpose i/o bit 1.6 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=fan_tach1 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 159 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description gp17 default = 0x01 on vtr por 0x07 (r/w) general purpose i/0 bit 1.7 bit[0] in/out : =1 input, =0 output bit[1] polarity :=1 invert, =0 no invert bit[2] alternate function select 1=fan_tach2 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp20 default = 0x04 on vtr por note 1 0x08 (r/w) general purpose i/0 bit 2.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ddcsda_5v 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp21 default = 0x04 on vtr por note 1 0x09 (r/w) general purpose i/o bit 2.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[3:2] alternate function select 11=reserved 10=either edge triggered input 0 (note 2) 01= ddcscl_5v 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp22 default = 0x04 on vtr por note 1 0x0a (r/w) general purpose i/o bit 2.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[3:2] alternate function select 11=reserved 10=either edge triggered input 0 (note 2) 01= ddcsda_3v 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp23 default = 0x04 on vtr por note 1 0x0b (r/w) general purpose i/o bit 2.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ddcscl_3v 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 160 smsc lpc47m172 datasheet name reg offset (type) description gp24 default = 0x05 on vtr por 0x0c (r/w) general purpose i/o bit 2.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ncdc_dwn_enab 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull n/a 0x0d-0x14 (r) bits[7:0] reserved ? reads return 0 gp1 default = 0x00 on vtr por 0x15 (r/w) general purpose i/o data register 1 bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 gp2 default = 0x00 on vtr por 0x16 (r/w) general purpose i/o data register 2 bit[0] gp20 bit[1] gp21 bit[2] gp22 bit[3] gp23 bit[4] gp24 bits[7:5] reserved n/a 0x17-0x1f (r) bits[7:0] reserved ? reads return 0 note 1: the in/out, polarity and output type select bits do not apply when ddcscl/ddcsda signals are selected. note 2: if the eeti function is selected for this gpio then both a high-to-low and low-to-high edge will set the pme and msc status bits.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 161 smsc/non-smsc register sets ( rev. 01-11-07) datasheet chapter 10 runtime register block runtime registers table 10.1 shows the runtime register summary. see table 10.2 - runtime register block runtime registers description. the runtime register bl ock runtime registers can only be accessed when ld_num bit in the test 7 configurat ion register is ?1?. see ?power control runtime registers? section and ?gpio runtime registers? section for description of these registers. note these offsets replace the register offsets defined in the power control logica l device and gpio logical device when ld_num bit is ?1? table 10.1 - runtime register block runtime registers summary register offset (hex) type pci reset vcc por vtr por soft reset register 00 r/w - - 0x00 - pme_sts 01-03 r - - - - reserved ? reads return 0 04 r/w - - 0x00 - pme_en 05-07 r - - - - reserved ? reads return 0 08 r/w - - 0x00 - pme_sts3 09 r/w - - 0x00 - pme_sts2 0a r/w - - 0x00 - pme_sts1 0b r - - - - reserved ? reads return 0 0c r/w - - 0x00 - pme_en3 0d r/w - - 0x00 - pme_en2 0e r/w - - 0x00 - pme_en1 0f r - - - - reserved ? reads return 0 10 r/w - - 0x03 - led 11 r/w - - 0x00 - keyboard scan code 12 r - - 0x00 - tach1 lsb 13 r - - 0x00 - tach1 msb 14 r - - 0x00 - tach2 lsb 15 r - - 0x00 - tach2 msb 16 r/w - - 0x80 - nio_pme register 17 r/w - - 0x00 - msc_sts 18 r/w 0x01 0x01 - - force disk change 19 r - - - - floppy data rate select shadow 1a r - - - - uart1 fifo control shadow 1b r/w 0xff 0xff - - interrupt generating register 1 1c r/w 0xff 0xff - - interrupt generating register 2 1d r - - - - uart2 fifo control shadow 1f r - - - - reserved ? reads return 0 20 r/w - - 0x01 - gp10 21 r/w - - 0x01 - gp11 22 r/w - - 0x01 - gp12 23 r/w - - 0x01 - gp13 24 r/w - - 0x01 - gp14
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 162 smsc lpc47m172 datasheet register offset (hex) type pci reset vcc por vtr por soft reset register 25 r/w - - 0x01 - gp15 26 r/w - - 0x01 - gp16 27 r/w - - 0x01 - gp17 28 r/w - - 0x04 - gp20 29 r/w - - 0x04 - gp21 2a r/w - - 0x04 - gp22 2b r/w - - 0x04 - gp23 2c r/w - - 0x05 - gp24 2d-34 r - - - - reserved ? reads return 0 35 r/w - - 0x00 - gp1 36 r/w - - 0x00 - gp2 37-3f r - - - - reserved ? reads return 0 table 10.2 - runtime register block runtime registers description name reg offset (type) description pme_sts default = 0x00 on vtr por 0x00 (r/w) bit[0] pme_status = 0 (default) = 1 set when lpc47m172 would normally assert the nio_pme signal, independent of the stat e of the pme_en bit. bit[7:1] reserved pme_status is not affected by vcc por, soft reset or hard reset. writing a ?1? to pme_status will clear it and cause the lpc47m172 to stop asserting nio_pme, in enabled. writi ng a ?0? to pme_status has no effect. n/a 0x01 ? 0x03 (r) bits[7:0] reserved ? reads return 0 pme_en default = 0x00 on vtr por 0x04 (r/w) bit[0] pme_en = 0 nio_pme signal assertion is disabled (default) = 1 enables lpc47m172 to assert nio_pme signal bit[7:1] reserved pme_en is not affected by vcc por, soft reset or hard reset n/a 0x05 ? 0x07 (r) bits[7:0] reserved ? reads return 0
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 163 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description pme_sts3 default = 0x00 on vtr por 0x08 (r/w) pme wake status register 3 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp20 bit[1] gp21 bit[2] gp22 bit[3] gp23 bits[7:4] reserved the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] wi ll clear it. writing a ?0 ? to any bit in pme wake status register has no effect. pme_sts2 default = 0x00 on vtr por 0x09 (r/w) pme wake status register 2 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] wi ll clear it. writing a ?0 ? to any bit in pme wake status register has no effect.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 164 smsc lpc47m172 datasheet name reg offset (type) description pme_sts1 default = 0x00 on vtr por 0x0a (r/w) pme wake status register 1 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] reserved (note 1) bit[1] ri2 bit[2] ri1 bit[3] kbd bit[4] mouse bit[5] spekey (wake on specific key) bit[6] fan_tach1 (note) bit[7] fan_tach2 (note) the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] wi ll clear it. writing a ?0 ? to any bit in pme wake status register has no effect. note: ? when the gp1x/fan_tachx pin is configured as a gpio (gpio control register bit 2 = 0), the asso ciated pme status bit will never be set. ? when the pin is configured for the tachometer function (gpio control register bit 2 = 1) and then the f unction is switched to the gpio function, the associated pme status bit will be cleared. n/a 0x0b (r) bits[7:0] reserved ? reads return 0 pme_en3 default = 0x00 on vtr por 0x0c (r/w) pme wake status register 3 this register is used to enable individual lpc47m172 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the sour ce will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] gp20 bit[1] gp21 bit[2] gp22 bit[3] gp23 bits[7:4] reserved the pme wake enable register is no t affected by vcc por, soft reset or hard reset.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 165 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description pme_en2 default = 0x00 on vtr por 0x0d (r/w) pme wake enable register 2 this register is used to enable individual lpc47m172 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the sour ce will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register wi ll indicate the state of the wake source but will not assert the nio_pme signal. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake enable register is no t affected by vcc por, soft reset or hard reset. pme_en1 default = 0x00 on vtr por 0x0e (r/w) pme wake enable register 1 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the sour ce will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register wi ll indicate the state of the wake source but will not assert the nio_pme signal. bit[0] reserved (note 1) bit[1] ri2 bit[2] ri1 bit[3] kbd bit[4] mouse bit[5] spekey (wake on specific key) bit[6] fan_tach1 bit[7] fan_tach2 the pme wake enable register is no t affected by vcc por, soft reset or hard reset. n/a 0x0f (r) bits[7:0] reserved ? reads return 0
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 166 smsc lpc47m172 datasheet name reg offset (type) description led default = 0x03 on vtr por 0x10 (r/w) led register bit[0] grn_ylw 0 = select ylw_led if nslp_s5 if high 1 = select grn_led if nslp_s5 is high bit[1] sdy_blk 0 = blink at 0.67 hz with 39.6% duty cycle (0.59375 sec high, 0.90625 low) if nslp_s5 is high 1 = steady if nslp_s5 is high bit[7:2] reserved keyboard scan code default = 0x00 on vtr por 0x11 (r/w) keyboard scan code bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code tach1 lsb default = 0x00 on vtr por 0x12 (r) this register is least significant 8- bit of the 16-bit fan tachometer 1 reading. bit[0] fan_tach1 reading bit 0 ? bit[7] fan_tach1 reading bit 7 tach1 msb default = 0x00 on vtr por 0x13 (r) this register is most significant 8- bit of the 16-bit fan tachometer 1 reading. bit[0] fan_tach1 reading bit 8 ? bit[7] fan_tach1 reading bit 15 tach2 lsb default = 0x00 on vtr por 0x14 (r) this register is least significant 8- bit of the 16-bit fan tachometer 2 reading. bit[0] fan_tach2 reading bit 0 ? bit[7] fan_tach2 reading bit 7 tach2 msb default = 0x00 on vtr por 0x15 (r) this register is most significant 8- bit of the 16-bit fan tachometer 2 reading. bit[0] fan_tach2 reading bit 8 ? bit[7] fan_tach2 reading bit 15 nio_pme register default = 0x80 on vtr por 0x16 (r/w) bit[0] reserved bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain (default) 0=push pull
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 167 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description msc_sts default = 0x00 on vtr por 0x17 (r/w) miscellaneous status register bits[1:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). bit[0] either edge triggered interrupt input 0 status. this bit is set when an edge occurs on the gp21 pin. bit[1] either edge triggered interrupt input 1 status. this bit is set when an edge occurs on the gp22 pin. bit[7:2] reserved. this bit always returns zero. force disk change default = 0x01 on vcc por 0x18 (r/w) force disk change bit[0] force disk change for fdc0 0=inactive 1=active bit[1] reserved force change 0 can be written to 1 but is not clearable by software. force change 0 is cleared on nstep and nds0 dskchg (fdc dir register, bit 7) = (nds0 and force change 0) or ndskchg setting the force disk change bit active ?1? forces the fdd ndskchg input active. bit[7:2] reserved floppy data rate select shadow 0x19 (r) floppy data rate select shadow bit[0] data rate select 0 bit[1] data rate select 1 bit[2] precomp 0 bit[3] precomp 1 bit[4] precomp 2 bit[5] reserved bit[6] power down bit[7] soft reset uart1 fifo control shadow 0x1a (r) uart fifo control shadow 1 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb)
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 168 smsc lpc47m172 datasheet name reg offset (type) description int_gen1 default = 0xff on vcc por and hard reset 0x1b (r/w) interrupt generating register 1 (note 2) 0=corresponding interrupt frame driven low in the ser irq stream. this must be enabled through the int_g configuration register. bit[0] reserved bit[1] nint1 bit[2] nint2 bit[3] nint3 bit[4] nint4 bit[5] nint5 bit[6] nint6 bit[7] nint7 note: to enable/disable this register see logical device a (0xf1) int_gen2 default = 0xff on vcc por and hard reset 0x1c (r/w) interrupt generating register 2 (note 2) 0=corresponding interrupt frame driven low in the ser irq stream. this must be enabled through the int_g configuration register. bit[0] nint8 bit[1] nint9 bit[2] nint10 bit[3] nint11 bit[4] nint12 bit[5] nint13 bit[6] nint14 bit[7] nint15 note: to enable/disable this register see logical device a (0xf1) n/a 0x1d-0x1f (r) bits[7:0] reserved ? reads return 0 uart2 fifo control shadow 0x1d (r) uart fifo control shadow 2 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) n/a 0x1f (r) bits[7:0] reserved ? reads return 0 gp10 default = 0x01 on vtr por 0x20 (r/w) general purpose i/o bit 1.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 169 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description gp11 default = 0x01 on vtr por 0x21 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp12 default = 0x01 on vtr por 0x22 (r/w) general purpose i/o bit 1.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp13 default = 0x01 on vtr por 0x23 (r/w) general purpose i/o bit 1.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp14 default = 0x01 on vtr por 0x24 (r/w) general purpose i/o bit 1.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp15 default = 0x01 on vtr por 0x25 (r/w) general purpose i/o bit 1.5 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp16 default = 0x01 on vtr por 0x26 (r/w) general purpose i/o bit 1.6 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=fan_tach1 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 170 smsc lpc47m172 datasheet name reg offset (type) description gp17 default = 0x01 on vtr por 0x27 (r/w) general purpose i/0 bit 1.7 bit[0] in/out : =1 input, =0 output bit[1] polarity :=1 invert, =0 no invert bit[2] alternate function select 1=fan_tach2 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp20 default = 0x04 on vtr por note 3 0x28 (r/w) general purpose i/0 bit 2.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ddcsda_5v 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp21 default = 0x04 on vtr por note 3 0x29 (r/w) general purpose i/o bit 2.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[3:2] alternate function select 11=reserved 10=either edge triggered input 0 (note 4) 01= ddcscl_5v 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp22 default = 0x04 on vtr por note 3 0x2a (r/w) general purpose i/o bit 2.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[3:2] alternate function select 11=reserved 10=either edge triggered input 0 (note 4) 01= ddcsda_3v 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 171 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg offset (type) description gp23 default = 0x04 on vtr por note 3 0x2b (r/w) general purpose i/o bit 2.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ddcscl_3v 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp24 default = 0x05 on vtr por 0x2c (r/w) general purpose i/o bit 2.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ncdc_dwn_enab 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull n/a 0x2d-0x34 (r) bits[7:0] reserved ? reads return 0 gp1 default = 0x00 on vtr por 0x35 (r/w) general purpose i/o data register 1 bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 gp2 default = 0x00 on vtr por 0x36 (r/w) general purpose i/o data register 2 bit[0] gp20 bit[1] gp21 bit[2] gp22 bit[3] gp23 bit[4] gp24 bits[7:5] reserved n/a 0x37-0x3f (r) bits[7:0] reserved ? reads return 0
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 172 smsc lpc47m172 datasheet chapter 11 configuration the configuration of the lpc47m172 is very flexib le and is based on the conf iguration architecture implemented in typical plug-and-play component s. the lpc47m172 is designed for motherboard applications in which the resources required by their components are known. with its flexible resource allocation architecture, the lpc47m172 allows the bios to assign resources at post. 11.1 system elements 11.1.1 primary configur ation address decoder after a hard reset (npci_reset pin asserted) or vcc power on reset the lpc47m172 is in the run mode with all logical devices disabled. the logical devices may be configured through two standard configuration i/o ports (index and data) by placing the lpc 47m172 into configuration mode. the bios uses these config uration ports to initialize the logical devices at post. the index and data ports are only valid when the lpc4 7m172 is in configuration mode. the config port?s i/o address is set to 0x02e at power-up. once powered up the configuration port base address can be changed through conf iguration registers cr26 and cr27. the index and data ports are effective only w hen the chip is in t he configuration state. port name base address type config port (note) 0x02e write index port (note) 0x02e read/write data port index port + 1 read/write note : the configuration port base address ca n be relocated through cr26 and cr27. 11.1.2 entering the c onfiguration state the device enters the configuration state when the following config key is successfully written to the config port. config key = <0x55> 11.1.3 exiting the c onfiguration state the device exits the configuration state when the following config key is successfully written to the config port. config key = <0xaa>
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 173 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 11.1.4 configuration sequence to program the configuratio n registers, the following sequence must be followed: 1. enter configuration mode 2. configure the configuration registers 3. exit configuration mode. 11.1.5 enter configuration mode to place the chip into the configur ation state the config key is sent to the chip?s config port. the config key consists of 0x55 written to the config port. once the conf iguration key is received correctly the chip enters into the configuration st ate (the auto config ports are enabled). 11.1.6 configuration mode the system sets the logical device information and activates desired logical devices through the index and data ports. in configuration mo de, the index port is located at the config port address and the data port is at index port address + 1. the desired configuration register s are accessed in two steps: a) write the index of the logical device number conf iguration register (i.e., 0x00 for fdc) to the index port and then write the number of the de sired logical device to the data port b) write the address of the desired c onfiguration register within the lo gical device to the index port and then write or read the configurati on register through the data port. note : if accessing the global configuration re gisters, step (a) is not required. 11.1.7 exit configuration mode to exit the configuration state t he system writes 0xaa to the config port. the chip returns to the run state. note : only two states are defined (run a nd configuration). in the run stat e the chip will always be ready to enter the confi guration state.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 174 smsc lpc47m172 datasheet 11.1.8 programming example the following is an example of a configuration program in intel 8086 assembly language. ;-------------------------------------------------. ; enter configuration mode | ;-------------------------------------------------? mov dx,02eh mov ax,055h out dx,al ;-----------------------------------------------. ; configure register cre0, | ; logical device 8 | ;-----------------------------------------------? mov dx,02eh mov al,07h out dx,al ;point to ld# config reg mov dx,02fh mov al, 08h out dx,al;point to logical device 8 ; mov dx,02eh mov al,e0h out dx,al ; point to cre0 mov dx,02fh mov al,02h out dx,al ; update cre0 ;------------------------------------------------. ; exit configuration mode | ;-----------------------------------------------? mov dx,02eh mov ax,0aah out dx,al notes: ? hard reset: npci_reset pin asserted ? soft reset: bit 0 of configurati on control register set to one ? all host accesses are blocked for 500s after vcc por (see power-up timing diagram) ld_num bit the ld_num bit in the test 7 global configuration register (0x29) is used to select between the logical device numbering in the lpc47m172. ld_num is det ermined by the state of pin 117 as described in chapter 2. see the test 7 register for ld_num bit description. table 11.1 and table 11.2 summarize the logical device registers when ld_num bit is 0 and 1.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 175 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 11.1 - lpc47m172 configuration registers summary, ld_num bit = 0 index type pci reset vcc por vtr por soft reset configuration register global configuration registers 0x02 w 0x00 0x00 0x00 - config control 0x03 r - - - - reserved ? reads return 0 0x07 r/w 0x00 0x00 0x00 0x00 logical device number 0x20 r 0x14 0x14 0x14 0x14 device id ? hard wired 0x21 r 0x04 0x04 0x04 0x04 device rev ? hard wired 0x22 r/w 0x00 0x00 0x00 0x00 power control 0x23 r - - - - reserved ? reads return 0 0x24 r/w 0x44 0x44 0x44 - osc 0x26 r/w 0x2e 0x2e - - configuration port address byte 0 (low byte) 0x27 r/w 0x00 0x00 - - configuration port address byte 1 (high byte) 0x28 r/w - 0x00 0x00 - test 8 0x29 r/w 0x00 0x00 0x00 - test 7 0x2a r/w - 0x00 0x00 - test 6 0x2b r/w - 0x00 0x00 - test 4 0x2c r/w - 0x00 0x00 - test 5 0x2d r/w - 0x00 0x00 - test 1 0x2e r/w - 0x00 0x00 - test 2 0x2f r/w - 0x00 0x00 - test 3 logical device 0 configuration registers (fdd) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x03 0x03 0x03 0x03 primary base i/o address high byte 0x61 r/w 0xf0 0xf0 0xf0 0xf0 primary base i/o address low byte 0x70 r/w 0x06 0x06 0x06 0x 06 primary interrupt select 0x74 r/w 0x02 0x02 0x02 0x02 dma channel select 0xf0 r/w 0x0e 0x0e 0x0e - fdd mode register 0xf1 r/w 0x00 0x00 0x00 - fdd option register 0xf2 r/w 0xff 0xff 0xff - fdd type register 0xf4 r/w 0x00 0x00 0x00 - fdd0 0xf8 r/w 0x24 0x24 0x24 - fdc mapping register logical device 1 configuration registers (parallel port) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select 0x74 r/w 0x04 0x04 0x04 0x04 dma channel select 0xf0 r/w 0x3c 0x3c 0x3c - parallel port mode register 0xf1 r/w 0x00 0x00 0x00 - parallel port mode register 2
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 176 smsc lpc47m172 datasheet index type pci reset vcc por vtr por soft reset configuration register 0xf8 r/w 0x08 0x08 0x08 - pp mapping register logical device 2 configuration registers (serial port 2) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 2 mode register 0xf1 r/w 0x02 0x02 0x02 - ir options register 0xf2 r/w 0x03 0x03 0x03 - ir half duplex timeout logical device 3 configuration registers (serial port 1) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 1 mode register logical device 4 configuration registers (power control) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0xf0 r/w - - 0x00 - clocki32 0xf1 r/w 0x00 0x00 0x00 0x00 int_g register logical device 5 configuration registers (mouse) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select logical device 6 configuration registers (keyboard) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 (note 1) - kreset and gatea20 select logical device 7 configuration registers (gpio) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte note : reserved registers are read-only, reads return 0. note 1: bits[7:5] of this register reset on vtr por only.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 177 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 11.2 - lpc47m172 configuration register summary, ld_num=1 index type pci reset vcc por vtr por soft reset configuration register global configuration registers 0x02 w 0x00 0x00 0x00 - config control 0x03 r - - - - reserved ? reads return 0 0x07 r/w 0x00 0x00 0x00 0x00 logical device number 0x20 r 0x14 0x14 0x14 0x14 device id ? hard wired 0x21 r 0x04 0x04 0x04 0x04 device rev ? hard wired 0x22 r/w 0x00 0x00 0x00 0x00 power control 0x23 r - - - - reserved ? reads return 0 0x24 r/w 0x44 0x44 0x44 - osc 0x26 r/w 0x2e 0x2e - - configuration port address byte 0 (low byte) 0x27 r/w 0x00 0x00 - - configuration port address byte 1 (high byte) 0x28 r/w - 0x00 0x00 - test 8 0x29 r/w 0x01 0x01 0x01 - test 7 0x2a r/w - 0x00 0x00 - test 6 0x2b r/w - 0x00 0x00 - test 4 0x2c r/w - 0x00 0x00 - test 5 0x2d r/w - 0x00 0x00 - test 1 0x2e r/w - 0x00 0x00 - test 2 0x2f r/w - 0x00 0x00 - test 3 logical device 0 configuration registers (fdd) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x03 0x03 0x03 0x03 primary base i/o address high byte 0x61 r/w 0xf0 0xf0 0xf0 0xf0 primary base i/o address low byte 0x70 r/w 0x06 0x06 0x06 0x 06 primary interrupt select 0x74 r/w 0x02 0x02 0x02 0x02 dma channel select 0xf0 r/w 0x0e 0x0e 0x0e - fdd mode register 0xf1 r/w 0x00 0x00 0x00 - fdd option register 0xf2 r/w 0xff 0xff 0xff - fdd type register 0xf4 r/w 0x00 0x00 0x00 - fdd0 0xf8 r/w 0x24 0x24 0x24 - test9 logical device 1 configuration registers (reserved) logical device 2 configuration registers (serial port 2) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 2 mode register 0xf1 r/w 0x02 0x02 0x02 - ir options register 0xf2 r/w 0x03 0x03 0x03 - ir half duplex timeout
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 178 smsc lpc47m172 datasheet index type pci reset vcc por vtr por soft reset configuration register logical device 3 configuration registers (parallel port) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select 0x74 r/w 0x04 0x04 0x04 0x04 dma channel select 0xf0 r/w 0x3c 0x3c 0x3c - parallel port mode register 0xf1 r/w 0x00 0x00 0x00 - parallel port mode register 2 0xf8 r/w 0x08 0x08 0x08 - test10 logical device 4 configuration registers (serial port 1) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 1 mode register logical device 5 configuration registers (reserved) logical device 6 configuration registers (reserved) logical device 7 configuration registers (keyboard) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x70 r/w 0x00 0x00 0x00 0x 00 primary interrupt select 0x72 r/w 0x00 0x00 0x00 0x00 secondary interrupt select 0xf0 r/w 0x00 0x00 0x00 (note 1) - kreset and gatea20 select logical device 8 configuration registers (reserved) logical device 9 configuration registers (reserved) logical device a configuration re gisters (runtime register block) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0xf0 r/w - - 0x00 - clocki32 0xf1 r/w 0x00 0x00 0x00 0x00 int_g register logical device b configuration registers (reserved) logical device c configuration registers (reserved) note: reserved registers are read-only, reads return 0. note 1: bits[7:6, 5 and 1] of kreset and gatea20 select register reset on vtr por only.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 179 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 11.2 chip level (global) cont rol/configuration registers[0x00-0x2f] the chip-level (global) registers lie in the address range [0x00-0x2f]. the design must use all 8 bits of the address port for register selection. all unimpl emented registers and bits ignore writes and return zero when read. the index port is used to select a configuration register in the chip . the data port is then used to access the selected register. these registers are accessible only in t he configuration mode. table 11.3 - chip level registers register address description chip (global) control registers 0x00 - 0x01 reserved - writes are ignored, reads return 0. config control default = 0x00 on vcc por, vtr por and hard reset 0x02 w the hardware automatically clears this bit after the write, there is no need for software to clear the bit. bit 0 = 1: soft reset. bits 7:1 reserved refer to the ?configuration registers? table for the soft reset value for each register. 0x03 - 0x06 reserved - writes are ignored, reads return 0 . logical device # default = 0x00 on vcc por, vtr por, soft reset and hard reset 0x07 r/w a write to this register selects the current logical device. this allows access to the control and configuration registers for each logical device. note: the activate command operates only on the selected logical device. card level reserved 0x08 - 0x1f reserved - writes are ignored, reads return 0 . chip level, smsc defined device id hard wired = 0x14 0x20 r a read only register which provides device identification. bits[7:0] = 0x 14 when read. device rev hard wired = current revision 0x21 r a read only register which provides device revision information. bits[7:0] = current revision when read.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 180 smsc lpc47m172 datasheet register address description chip (global) control registers powercontrol default = 0x00 on vcc por, vtr por, soft reset and hard reset 0x22 r/w bit[0] fdc power bit[1] reserved bit[2] reserved bit[3] parallel port power bit[4] serial port 1 power bit[5] serial port 2 power bit[6] reserved bit[7] reserved 0 = power off or disabled 1 = power on or enabled 0x23 r reserved - writes are ignored, reads return 0. osc default = 0x44, on vcc por, vtr por and hard reset 0x24 r/w bit[0] reserved bit [1] pll control = 0 pll is on (backward compatible) = 1 pll is off bits[3:2] osc = 01 osc is on, brg clock is on. = 10 same as above (01) case. = 00 osc is on, brg clock enabled. = 11 osc is off, brg cl ock is disabled. bit [5:4] reserved, set to zero bit [6] 16-bit address qualification = 0 12-bit address qualification = 1 16-bit address qualification note: for normal operation, bit 6 should be set. bit[7] reserved chip level vendor defined 0x25 reserved - writes are ignored, reads return 0. configuration address byte 0 default =0x2e on vcc por and hard reset 0x26 bit[7:1] configuration address bits [7:1] bit[0] = 0 configuration address byte 1 default = 0x00 on vcc por and hard reset 0x27 bit[7:0] configuration address bits [15:8] see note 1 test 8 default = 0x00 on vcc por and vtr por 0x28 r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 181 smsc/non-smsc register sets ( rev. 01-11-07) datasheet register address description chip (global) control registers test 7 default = 0x00 (when pin 117 is nc) 0x01(when pin 117 is connected to vtr) on vcc por, vtr por and hard reset 0x29 r/w bit[0] ld_num = 0 new ld numbering (selected when pin 117 is nc) = 1 smsc ld numbering (selected when pin 117 is connected to vtr) pin 117 is used to select the mode of the logical device numbering. this pin affects the ld_num bit as follows: ? the pin has an internal pull-down resistor that selects the non-smsc mode. to select this mode, the pin should be left unconnected. this configuration clears the ld_num bit to ?0? and the associated functionality corresponds to the existing functionality in the part when the ld_num bit=0. ? connecting this pin to vtr will select the smsc mode of the logical device numbering. this configuration sets the ld_num bit to ?1? and the associated functionality corresponds to the existing functionality in the part when the ld_num bit=1. bits[7:1] reserved test 6 default = 0x00, on vcc por and vtr por 0x2a r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 4 default = 0x00, on vcc por and vtr por 0x2b r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 5 default = 0x00, on vcc por and vtr por 0x2c r/w bit[7] test mode: reserved for smsc. users should not write to this bit, may produce undesired results. bit[6] 8042 reset: 1 = put the 8042 into reset 0 = take the 8042 out of reset bits[5:0] test mode: reserved for smsc. users should not write to this bit, may produce undesired results. test 1 default = 0x00, on vcc por and vtr por 0x2d r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 2 default = 0x00, on vcc por and vtr por 0x2e r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 182 smsc lpc47m172 datasheet register address description chip (global) control registers test 3 default = 0x00, on vcc por and vtr por 0x2f r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. note 1: to allow the selection of the configuration address to a user defined location, these configuration address bytes are used. there is no restriction on the addre ss chosen, except that a0 is 0, that is, the address must be on an even byte boundary. as soon as both by tes are changed, the confi guration space is moved to the specified locati on with no delay ( note: write byte 0, then byte 1; writing cr27 changes the base address). 11.3 logical device configurati on/control registers [0x30-0xff] these registers are used to access the registers that are assigned to each logical device. the logical devices are floppy, parallel, serial port, keyboard controller, power control and gpio. a separate set (bank) of control and config uration registers exists for each logical device and is selected with the logical device # register (0x07). the index port is used to select a specific logical device register. these registers are then accessed through the data port. the logical device registers are accessible only when the device is in the configur ation state. the logical register addresses are shown in the table below. table 11.4 - logical device registers logical device register address description activate default = 0x00 on vcc por, vtr por, hard reset and soft reset (0x30) bits[7:1] reserved, set to zero. bit[0] = 1 activates the logical device currently selected through the logical device # register. = 0 logical device currently selected is inactive note: a logical device will be active and powered up according to the following equation unless otherwise specified: device on (active) = (activate bit set or pwr/control bit set). the logical device?s activate bit and its pwr/control bit are linked such that setting or clearing one sets or clears the other. logical device control (0x31-0x37) reserved ? writes are ignored, reads return 0. logical device control (0x38-0x3f) vendor defined - reserved - writes are ignored, reads return 0. memory base address (0x40-0x5f) reserved ? writes are ignored, reads return 0.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 183 smsc/non-smsc register sets ( rev. 01-11-07) datasheet logical device register address description i/o base address (see device base i/o address table) default = 0x00 on vcc por, vtr por, hard reset and soft reset (0x60-0x6f) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] registers 0x60 and 0x61 set the base address for the device. if more than one base address is required, the second base address is set by registers 0x62 and 0x63. refer to table 11.7 and table 11.8 for the number of base address registers used by each device. unused registers will ignore writes and return zero when read. note: if the i/o base addr of the logical device is not within the base i/o range as shown in the logical device i/o map, then read or write is not valid and is ignored. interrupt select defaults : 0x70 = 0x00 or 0x06 (note) on vcc por, vtr por, hard reset and soft reset 0x72 = 0x00, on vcc por, vtr por, hard reset and soft reset (0x70,0x72) 0x70 is implemented for each logical device. refer to interrupt configuration register description. only the keyboard controller uses interrupt select register 0x72. unused register (0x72) will ignore writes and return zero when read. interrupts default to edge high (isa compatible). refer to table 11.5 note: the default value of the primary interrupt select register for logical device 0 is 0x06. (0x71,0x73) reserved - not implemented. these register locations ignore writes and return zero when read. dma channel select default = 0x02 or 0x04 (note) on vcc por, vtr por, hard reset and soft reset (0x74,0x75) only 0x74 is implemented for fdc and parallel port. 0x75 is not implemented and ignores writes and returns zero when read. refer to table 11.6. note: the default value of the dma channel select register for logical device 0 (fdd) is 0x02 and for logical device 4 (uart) is 0x04. 32-bit memory space configuration (0x76-0xa8) reserved - not implemented. these register locations ignore writes and return zero when read. logical device (0xa9-0xdf) reserved - not implemented. these register locations ignore writes and return zero when read. logical device configuration (0xe0-0xfe) reserved ? vendor defined (see smsc defined logical device configuration registers). reserved 0xff reserved
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 184 smsc lpc47m172 datasheet table 11.5 - primary interrupt select configuration register description name reg index definition primary interrupt select default=0x00 or 0x06 (note 1) on vcc por, vtr por, hard reset and soft reset 0x70 (r/w) bits[3:0] selects which interrupt is used for the primary interrupt. 0x00= no interrupt selected 0x01= irq1 0x02= irq2 0x03= irq3 0x04= irq4 0x05= irq5 0x06= irq6 0x07= irq7 0x08= irq8 0x09= irq9 0x0a= irq10 0x0b= irq11 0x0c= irq12 0x0d= irq13 0x0e= irq14 0x0f= irq15 note: all interrupts are edge high (except ecp/epp) notes: ? an interrupt is activated by setting the interrupt request level select 0 register to a non-zero value and : - for the fdc logical device by setting dmaen, bit d3 of the digital output register. - for the pp logical device by setting irqe, bit d4 of the control port and in addition - for the pp logical device in ecp mode by clearing serviceintr, bit d2 of the ecr. - for the serial port logical device by setting any combination of bits d0-d3 in the ier - and by setting the out2 bit in the uart's modem control (mcr) register. - for the kybd logical device (refer to the kybd controller section of this spec). ? irqs are disabled if not used/selected by any logical device. refer to note a. ? all irq?s are available in serial irq mode. note 1: the default value of the primary interrupt sele ct register for logical device 0 is 0x06. table 11.6 - dma channel select configuration register description name reg index definition dma channel select default=0x02 or 0x04 (note 1) on vcc por, vtr por, hard reset and soft reset 0x74 (r/w) bits[2:0] select the dma channel. 0x00= reserved 0x01= dma1 0x02= dma2 0x03= dma3 0x04-0x07= no dma active notes: ? a dma channel is activated by setting the dm a channel select register to [0x01-0x03] and : - for the fdc logical device by setting dmaen, bit d3 of the digital output register.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 185 smsc/non-smsc register sets ( rev. 01-11-07) datasheet - for the pp logical device in ecp mode by setting dmaen, bit d3 of the ecr. ? the dma channel must be disabled if not used/selected by any logical device. refer to note a. note 1: the default value of the dma channel select register for logical device 0 (fdd) is 0x02 and for logical device 3 is 0x04. note a. logical device irq and dma operation 1. irq and dma enable and disable: any time the irq or dma channel for a logical block is disabled by a register bit in that logical block, the irq and/or dma channel must be disabled. this is in addition to the irq and dma channel disabled by the configuration registers (active bit or address not valid). a. fdc: for the following cases, the irq and dma channel used by the fdc are disabled. digital output register (base+2) bit d3 (dmaen) set to ?0?. the fdc is in power down (disabled). b. serial port: modem control register (mcr) bit d2 (out2) - when out2 is a logic ?0?, the serial port interrupt is disabled. c. parallel port: i. spp and epp modes: control port (base+2) bit d4 (irqe) set to ?0?, irq is disabled. ii. ecp mode: (1) (dma) dmaen from ecr register. see table. (2) irq - see table. mode (from ecr register) irq controlled by dma controlled by 000 printer irqe dmaen 001 spp irqe dmaen 010 fifo (on) dmaen 011 ecp (on) dmaen 100 epp irqe dmaen 101 res irqe dmaen 110 test (on) dmaen 111 config irqe dmaen d. keyboard controller: refer to the kbd section of this spec.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 186 smsc lpc47m172 datasheet 11.4 logical device i/o address table 11.7 and table 11.8 summarize the logical device i/o addresses when ld_num bit is 0 and 1. table 11.7 - logical device i/o address, ld_num bit = 0 logical device number logical device register index base i/o range (note 1) fixed base offsets 0x00 fdc 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : sra +1 : srb +2 : dor +3 : tsr +4 : msr/dsr +5 : fifo +7 : dir/ccr [0x0100:0x0ffc] on 4 byte boundaries (epp not supported) or [0x0100:0x0ff8] on 8 byte boundaries +0 : data/ecpafifo +1 : status +2 : control +400h : cfifo/ecpdfifo/tfifo/cnfga +401h : cnfgb +402h : ecr 0x01 parallel port 0x60,0x61 (all modes supported, epp is only available when the base address is on an 8- byte boundary) +3 : epp address +4 : epp data 0 +5 : epp data 1 +6 : epp data 2 +7 : epp data 3 0x02 serial port 2 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x03 serial port 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x04 power control 0x60,0x61 [0x0000:0x0fe0] on 32-byte boundaries +00 : pme status . . . +1f : reserved (see table 8.1 for full list) 0x05 mouse n/a not relocatable +0 : data register +4 : command/status reg. 0x06 kybd n/a not relocatable fixed base address: 60,64 +0 : data register +4 : command/status reg. 0x07 gpio 0x60,0x61 [0x0000:0x0fe0] on 32-byte boundaries +00 : gp10 . . +1f : reserved (see table 9.1 for full list)
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 187 smsc/non-smsc register sets ( rev. 01-11-07) datasheet logical device number logical device register index base i/o range (note 1) fixed base offsets config. port config. port 0x26, 0x27 0x0100:0x0ffe on 2 byte boundaries see configuration register summary table. accessed through the index and data ports located at the configuration port address and the configuration port address +1 respectively. note 1 : this chip uses address bits [a11:a0] to decode the base address of each of its logical devices. bit 6 of the osc global configuration register (cr24) must be set to ?1? and address bits [a15:a12] must be ?0? for 16 bit address qualification. table 11.8 - logical device i/o address, ld_num bit = 1 logical device number logical device register index base i/o range (note 1) fixed base offsets 0x00 fdc 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : sra +1 : srb +2 : dor +3 : tsr +4 : msr/dsr +5 : fifo +7 : dir/ccr 0x01 reserved n/a n/a n/a 0x02 serial port 2 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr [0x0100:0x0ffc] on 4 byte boundaries (epp not supported) or [0x0100:0x0ff8] on 8 byte boundaries +0 : data/ecpafifo +1 : status +2 : control +400h : cfifo/ecpdfifo/tfifo/cnfga +401h : cnfgb +402h : ecr 0x03 parallel port 0x60,0x61 (all modes supported, epp is only available when the base address is on an 8- byte boundary) +3 : epp address +4 : epp data 0 +5 : epp data 1 +6 : epp data 2 +7 : epp data 3
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 188 smsc lpc47m172 datasheet logical device number logical device register index base i/o range (note 1) fixed base offsets 0x04 serial port 1 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x05 reserved n/a n/a n/a 0x06 reserved n/a n/a n/a 0x07 kybd n/a not relocatable fixed base address: 60,64 +0 : data register +4 : command/status reg. 0x08 reserved n/a n/a n/a 0x09 reserved n/a n/a n/a 0x0a runtime register block 0x60,0x61 [0x0000:0x0fc0] on 64-byte boundaries +00 : pme status . . . +3f : reserved (see table 10.1 for full list) 0x0b reserved n/a n/a n/a config. port config. port 0x26, 0x27 0x0100:0x0ffe on 2 byte boundaries see configuration register summary table. accessed through the index and data ports located at the configuration port address and the configuration port address +1 respectively. note 1: this chip uses address bits [a11:a0] to decode the base address of each of its logical devices. bit 6 of the osc global configuration register (cr24) must be set to ?1? and address bits [a15:a12] must be ?0? for 16 bit address qualification.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 189 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 11.5 logical device configuration registers the logical device configuration registers reset to th eir default values only on hard resets generated by vcc or vtr por (as shown) or the npci_r eset signal. these registers are not affected by soft resets. table 11.9 - floppy disk controller logical device configuration registers name reg index definition fdd mode register default = 0x0e on vcc por, vtr por and hard reset 0xf0 r/w bit[0] floppy mode = 0 normal floppy mode (default) = 1 enhanced floppy mode 2 (os2) bit[1] fdc dma mode = 0 burst mode is enabled = 1 non-burst mode (default) bit[3:2] interface mode = 11 at mode (default) = 10 (reserved) = 01 ps/2 = 00 model 30 bit[4] fdc_swap 0 = do not swap (default) 1 = swap drive 0 (nds, nmtr pins) with drive 1 (nds, nmtr pins) bit[5] reserved, set to zero bit[6] fdc output type control = 0 fdc outputs are od12 open drain (default) = 1 fdc outputs are o12 push-pull bit[7] fdc output control = 0 fdc outputs active (default) = 1 fdc outputs tri-stated fdd option register default = 0x00 on vcc por, vtr por and hard reset 0xf1 r/w bit[0] forced write protect = 0 inactive (default) = 1 fdd nwrtprt input is forced active when either of the drives has been selected. nwrtprt (to the fdc core) = wp (fdc sra register, bit 1) = (nds0 and forced write protect) or (nds1 and forced write protect) or nwrtprt (from the fdd interface) bit[1] reserved bits[3:2] density select = 00 normal (default) = 01 normal (reserved for users) = 10 1 (forced to logic ?1?) = 11 0 (forced to logic ?0?) bit[7:4] reserved.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 190 smsc lpc47m172 datasheet name reg index definition fdd type register default = 0xff on vcc por, vtr por and hard reset 0xf2 r/w bits[1:0] floppy drive a type bits[3:2] reserved (could be used to store floppy drive b type) bits[5:4] reserved (could be used to store floppy drive c type) bits[7:6] reserved (could be used to store floppy drive d type) 0xf3 r reserved, read as 0 (read only) fdd0 default = 0x00 on vcc por, vtr por and hard reset 0xf4 r/w bits[1:0] drive type select: dt1, dt0 bits[2] read as 0 (read only) bits[4:3] data rate table select: drt1, drt0 bits[5] read as 0 (read only) bits[6] precompensation disable pts =0 use precompensation =1 no precompensation bits[7] read as 0 (read only) 0xf5 r reserved, read as 0 (read only) test9 default = 0x24 on vcc por, vtr por and hard reset 0xf8 r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. table 11.10 - serial port 2 logical device configuration registers name reg index definition serial port 2 mode register default = 0x00 on vcc por, vtr por and hard reset 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit[7:2] reserved, set to zero
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 191 smsc/non-smsc register sets ( rev. 01-11-07) datasheet name reg index definition ir option register default = 0x02 on vcc por, vtr por and hard reset 0xf1 r/w bit[0] receive polarity = 0 active high (default) = 1 active low bit[1] transmit polarity = 0 active high = 1 active low (default) bit[2] duplex select = 0 full duplex (default) = 1 half duplex bits[5:3] ir mode = 000 standard com functionality (default) = 001 irda = 010 ask-ir = 011 reserved = 1xx reserved bit[6] ir location mux = 0 use serial port txd2 and rxd2 (default). the irtx2 pin is low. = 1 use alternate irrx2 and irtx2 pins. the txd2 pin is tri-state. bit[7] reserved, write 0. ir half duplex timeout default = 0x03 on vcc por, vtr por and hard reset 0xf2 bits [7:0] these bits set the half duplex time-out for the ir port. this value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec . . . table 11.11 - parallel port logical device configuration registers name reg index definition pp mode register default = 0x3c on vcc por, vtr por and hard reset 0xf0 r/w bits[2:0] parallel port mode = 100 printer mode (default) = 000 standard and bi-directional (spp) mode = 001 epp-1.9 and spp mode = 101 epp-1.7 and spp mode = 010 ecp mode = 011 ecp and epp-1.9 mode = 111 ecp and epp-1.7 mode bit[6:3] ecp fifo threshold 0111b (default) bit[7] pp interrupt type not valid when the parallel port is in the printer mode (100) or the standard & bi-directional mode (000). = 1 pulsed low, released to high-z. = 0 irq follows nack when parallel port in epp mode or [printer,spp, epp] under ecp. irq level type when the parallel port is in ecp, test, or centronics fifo mode.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 192 smsc lpc47m172 datasheet name reg index definition pp mode register 2 default = 0x00 on vcc por, vtr por and hard reset 0xf1 r/w bits[3:0] reserved. set to zero bit [4] timeout_select = 0 tmout (epp status reg.) cleared on write of ?1? to tmout. = 1 tmout cleared on trailing edge of read of epp status reg. bits[7:5] reserved. set to zero. test10 default = 0x08 on vcc por, vtr por and hard reset 0xf8 r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. table 11.12 - serial port 1 logical device configuration registers name reg index definition serial port 1 mode register default = 0x00 on vcc por, vtr por and hard reset 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit[6:2] reserved, set to zero bit[7] share irq =0 uarts use different irqs =1 uarts share a common irq see note 1 below. note 1: to properly share and irq, 1. configure uart1 (or uart2) to use the desired irq. 2. configure uart2 (or uart1) to use no irq selected. 3. set the share irq bit. note: if both uarts are configured to use different irqs and the share irq bit is set, then both of the uart irqs will assert when either uart generates an interrupt.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 193 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 11.13 - keyboard logical device configuration registers name reg index definition krst_ga20 default = 0x00 on vcc por, vtr por and hard reset bits[7:5] reset on vtr por only 0xf0 r/w kreset and gatea20 select bit[7] iso_mode = 0 mode 1 (default) ? isolate the 8042 in hardware while the nlpcpd signal is active or when the keyboard and mouse isolation bits are set by software. = 1 mode 2 ? keyboard and mouse isolation bits set by software only. note: the input path to the 8042 is also isolated while the nlpcpd signal is active. bit[6] m_iso. enables/disables isolation of mouse signals into 8042. does not affect mdat signal to mouse wakeup (pme) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 bit[5] k_iso. enables/disables isolation of keyboard signals into 8042. does not affect kdat signal to keyboard wakeup (pme) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 bit[4] mlatch = 0 mint is the 8042 mint anded with latched mint (default) = 1 mint is the latched 8042 mint bit[3] klatch = 0 kint is the 8042 kint anded with latched kint (default) = 1 kint is the latched 8042 kint bit[2] port 92 select = 0 port 92 disabled = 1 port 92 enabled bit[1] reserved bit[0] reserved table 11.14 - power control/runtime register block logical device configuration registers name reg index definition clocki32 default = 0x00 on vtr por 0xf0 (r/w) bit[0] (clk32_prsn) 0=32khz clock is connected to the clki32 pin (default) 1=32khz clock is not connected to the clki32 pin (pin is grounded) bit[1] spekey_en. this bit is used to turn the logic for the ?wake on specific key? feature on and off. it will disable the 32khz clock input to the logic when turned off. the logic will draw no power when disabled. 0= ?wake on specific key? logic is on (default) 1= ?wake on specific key? logic is off bits[7:2] are reserved
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 194 smsc lpc47m172 datasheet name reg index definition int_g default = 0x00 on vcc por, vtr por, hard reset and soft reset 0xf1 r/w bit[7:1] reserved bit[0] int_g enable 0 = disable interrupt generating registers (int_genx) from affecting the serial irq stream 1 = enable interrupt generating registers to drive one or more frames low in the ser irq stream note: see runtime registers at offset 0x1b and 0x1c for configuring interrupt generating registers.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 195 smsc/non-smsc register sets ( rev. 01-11-07) datasheet chapter 12 electrical characteristics 12.1 maximum guaranteed ratings maximum 3. 3 supply ............................................................................................................. ............... +4.1v maximum 5v supply .............................................................................................................. ............... +6.0v voltage on any 3.3v pin, with respect to ground ......................................................................... -0.5 to 5.5v voltage on any 5v pin, with respect to gr ound ............................................................................ -0.5 t o 5.5v operating temper ature range .................................................................................................. 0 o c to +70 o c storage temperatur e range .................................................................................................. -55 o to +150 o c lead temperature range (l ead-free, p/n lpc47n17 2-nw) ..................refer to jedec spec. j-std-020b lead temperature range (leaded, p/n lpc47n1 72-nr) ......................re fer to jedec spec. j-std-020b note: stresses above those listed above and below could caus e permanent damage to the device. this is a stress rating only and functional operation of the devic e at any other condition above those indicated in the operation sections of this specific ation is not implied. when poweri ng this device from laboratory or system power supplies, it is impor tant that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit vo ltage spikes on their output s when the ac power is switched on or off. in addition, vo ltage transients on the ac power li ne may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. 12.2 operational dc characteristics table 12.1 - operational dc characteristics (t a = 0 o c to 70 o c) parameter symbol min typ max units comments i input buffer low input level high input level v il v ih 2.0 0.8 5.5 v v ttl levels ttl levels ipu input buffer low input level high input level pull-up v il v ih pu 2.0 30 0.8 5.5 v v ua ttl levels ttl levels is input buffer low input level high input level schmitt trigger hystersis v il v ih v hys 2.2 250 0.8 5.5 v v mv schmitt trigger schmitt trigger
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 196 smsc lpc47m172 datasheet parameter symbol min typ max units comments is_400 input buffer low input level high input level schmitt trigger hystersis v il v ih v hys 2.2 400 0.8 5.5 v v mv schmitt trigger schmitt trigger ispu_400 input buffer low input level high input level schmitt trigger hystersis pull-up input low current input high current v il v ih v hys pu ileak il ileak ih 2.2 -26 400 30 0.8 5.5 1 -88 v v mv ua ua ua schmitt trigger schmitt trigger v in = vtr v in = 0v ao analog output buffer for ref5v_out low output level high output level for ref5v_stby low output level high output level v ol v oh v ol v oh vref3in -0.15 vtr-0.15 0.4 vref3in +0.15 0.4 vtr+ 0.15 v v v v vcc5v>1.5v, vcc5v>vcc + 0.15; vcc>1.5v, vcc>vcc5v + 0.15; i oh = -3.3ma v_5p0_stby>1.5v, v_5p0_stby>vtr + 0.15; vtr>1.5v, vtr>v_5p0_stby + 0.15; i oh = -3.3ma o8 output buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 8ma i oh = -4ma od8 output buffer low output level high output level v ol v oh 0.4 vcc+10% v v i ol = 8ma open-drain
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 197 smsc/non-smsc register sets ( rev. 01-11-07) datasheet parameter symbol min typ max units comments o12 output buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 12ma i oh = -6ma od12 output buffer low output level high output level v ol v oh 0.4 vcc+10% v v i ol = 12ma open-drain op14 output buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 14ma i oh = -14ma od24 output buffer low output level high output level v ol v oh 0.4 vcc+10% v v i ol = 24ma open-drain io8 input/output buffer low input level high input level low output level high output level v il v ih v ol v oh 2.0 2.4 0.8 5.5 0.4 v v v v ttl levels ttl levels i ol = 8ma i oh = -4ma iso8 input/output buffer low input level high input level schmitt trigger hystersis low output level high output level v il v ih v hys v ol v oh 2.2 2.4 250 0.8 5.5 0.4 v v mv v schmitt trigger schmitt trigger i ol = 8ma i oh = -4ma
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 198 smsc lpc47m172 datasheet parameter symbol min typ max units comments isod8 input/output buffer low input level high input level schmitt trigger hystersis low output level high output level v il v ih v hys v ol v oh 2.2 250 0.8 5.5 0.4 vcc+10% v v mv v v schmitt trigger schmitt trigger i ol = 8ma open-drain, vcc = 5v max ipdo8 input buffer low input level high input level pull-down low output level high output level v il v ih pd v ol v oh 2.0 30 0.8 5.5 0.4 vcc+10% v v ua v v ttl levels ttl levels i ol = 8ma i oh = -4ma io12 input/output buffer low input level high input level low output level high output level v il v ih v ol v oh 2.0 2.4 0.8 5.5 0.4 v v v v ttl levels ttl levels i ol = 12ma i oh = -6ma iop14 input/output buffer low input level high input level low output level high output level v il v ih v ol v oh 2.0 2.4 0.8 5.5 0.4 v v v v ttl levels ttl levels i ol = 14ma i oh = -14ma io_sw input/output special type pins of this type are connected in pairs through a switch. the switch provides a 25 ohm (max) resistance to ground when closed. see smbus isolation circuitry and voltage translation circuit sections for a description. note: vcc=5v max.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 199 smsc/non-smsc register sets ( rev. 01-11-07) datasheet parameter symbol min typ max units comments iod24 input/output buffer low input level high input level low output level high output level v il v ih v ol v oh 2.0 0.8 5.5 0.4 vcc+10% v v v v ttl levels ttl levels i ol = 24ma open-drain pci type buffers (pci_iclk, pci_i, pci_o, pci_io) 3.3v pci 2.1 compatible. leakage current (all except is, is_400, ispu_400, isod8, ao, o8_3v and pci buffers) input high current input low current ileak ih ileak il 10 -10 ua ua v in = vcc v in = 0v leakage current (is, is_400, ispu_400 and isod8 buffers) input high leakage current input low leakage current ileak ih ileak il 1 -1 ua ua v in = vcc v in = 0v leakage current (ao buffer) input high leakage current input low leakage current ileak ih ileak il 20 -20 ua ua v in = vcc v in = 0v leakage current (pci buffers and nrsmrst) input high leakage current input low leakage current ileak ih ileak il 10 -10 a a v cc = 0v and v cc = 3.3v v in = 3.6v max v in = 0v backdrive protect/chiprotect (all except pci buffers and nrsmrst) input high leakage current input low leakage current ileak ih ileak il 10 -10 a a v cc = 0v v in = 5.5v max v in = 0v
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 200 smsc lpc47m172 datasheet parameter symbol min typ max units comments 5v tolerant pins (all except pci buffers and nrsmrst) input high leakage current input low leakage current ileak ih ileak il 10 -10 a a v cc = 0v v in = 5.5v max v in = 0v 3.3v main supply voltage vcc 3.0 3.3 3.6 v vcc must not be greater than 0.5v above vtr 3.3v main supply current i cc3 10 15 ma all outputs open, all inputs transitioning to/from 0v from/to 3.3v 3.3v standby supply current i tr3 0.2 2 ma all outputs open, all inputs transitioning to/from 0v from/to 3.3v 5v standby supply voltage v_5p0_s tby 4.75 5.25 v 5v standby supply current i tr5 1 3 ma note: all leakage currents are measured with pins in high impedance. 12.3 standby power requirements this includes only signals that are outputs and source standby current (no od outputs). internal pull-ups are ignored due to their small contribution. external pull-ups are not in this analysis because they do not cause lpc47m172 to draw a discernable amount of additional power. application note: the following pins are powered by vtr. if configured as output pins , the vtr current will increase if these pins are sourcing current into a load. the board designer must make allowances for this additional current based upon this board design and the loads these pins are driving. table 12.2 - s3-s5 standby current symbol type stby max. current (ma) name and function ref5v_stby ao 3.3 standby reference output ncdc_dwn_enab/gp24 io12 6 codec down enable/gpio ncdc_dwn_rst o12 6 codec down reset npcirst_out op14 14 3.3v buffered copy of npci_reset npcirst_out2 op14 14 second 3.3v buffered copy of npci_reset nio_pme o8/od8 4 power management events latched_bf_cut op14 0 signal only on for a short period of time pwrgd_3v o8 4 power good signal nrsmrst o8 4 reset for the ich resume well gp10-gp17, gp20-gp23 io8 48 12 gpios total 103.3
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 201 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 12.4 capacitance values for pins capacitance t a = 25 o c; fc = 1mhz; v cc = 3.3v 10% limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except pin under test tied to ac ground note: the input capacitance of a port is measured at the connector pins.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 202 smsc lpc47m172 datasheet chapter 13 timing diagrams for the timing diagrams shown, the following capacitive loads are used on outputs. name capacitance total (pf) ser_irq 50 lad [3:0] 50 nldrq 50 ndir 240 nstep 240 nds0 240 pd[0:7] 240 nstrobe 240 nalf 240 kdat 240 kclk 240 mdat 240 mclk 240 txd 50 ylw_led 50 grn_led 50 nide_rstdrv 40 npcirst_out 40 npcirst_out2 40 ps_on 50 sck_bjt_gate 50 pwrgd_3v 50 ncdc_dwn_enab/ gp24 50 ncdc_dwn_rst 50
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 203 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t3 vcc all host a ccesses t2 t1 figure 13.1 - power-up timing name description min typ max units t1 vcc slew from 2.7v to 0v 300 us t2 vcc slew from 0v to 2.7v 100 us t3 all host accesses after powerup (note 1) 125 500 us note 1: internal write-protection period after vcc passes 2.7 volts on power-up
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 204 smsc lpc47m172 datasheet t1 t2 t2 clocki figure 13.2 - input clock timing name description min typ max units t1 clock cycle time for 14.318mhz 69.84 ns t2 clock high time/low time for 14.318mhz 20 35 ns t1 clock cycle time for 32khz 31.25 s t2 clock high time/low time for 32khz 15.63 s clock rise time/fall time (not shown) 5 ns t1 t3 t2 pci_clk t5 t4 figure 13.3 - pci clock timing name description min typ max units t1 period 30 33.3 nsec t2 high time 12 nsec t3 low time 12 nsec t4 rise time 3 nsec t5 fall time 3 nsec t1 npci_reset figure 13.4 - reset timing name description min typ max units t1 npci_reset width 1 ms
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 205 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t3 t2 t1 clk output delay tri-state output figure 13.5 - output timing measu rement conditions, lpc signals name description min typ max units t1 clk to signal valid delay ? bused signals 2 11 ns t2 float to active delay 2 11 ns t3 active to float delay 28 ns inputs valid t2 t1 clk input figure 13.6 - input timing measure ment conditions, lpc signals name description min typ max units t1 input set up time to clk ? bused signals 7 ns t2 input hold time from clk 0 ns l1 l2 a ddress data tar sync=0110 l3 tar pci_clk nlframe lad[3:0] note: l1=start; l2=cyctyp+dir; l3=sync of 0000 figure 13.7 - i/o write
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 206 smsc lpc47m172 datasheet l1 l2 a ddress tar sync=0110 l3 data tar pci_clk nlframe lad[3:0] note: l1=start; l2=cyctyp+dir; l3=sync of 0000 figure 13.8 - i/o read start msb lsb a ct pci_clk nldrq figure 13.9 - dma request assertion through nldrq start c+d chl size tar sync=0101 l1 data tar pci_clk lframe# lad[3:0] note: l1=sync of 0000 figure 13.10 - dma write (first byte) start c+d chl size data tar sync=0101 l1 tar pci_clk nlframe lad[3:0] note: l1=sync of 0000 figure 13.11 - dma read (first byte)
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 207 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t3 t1 t2 t4 t5 t6 t7 t8 ndir nstep nds0 nindex nrdata nwdata t9 figure 13.12 - floppy disk drive timing (at mode only) name description min typ max units t1 ndir set up to step low 4 x* t2 nstep active time low 24 x* t3 ndir hold time after nstep 96 x* t4 nstep cycle time 132 x* t5 nds0 hold time from nstep low (note) 20 x* t6 nindex pulse width 2 x* t7 nrdata active time low 40 ns t8 nwdata write data width low .5 y* t9 nds0 setup time ndir low (note) 0 ns notes: ? *x specifies one mclk period and y specifies one wclk period. mclk = 16 x data rate (at 500 kb/s mclk = 8 mhz) wclk = 2 x data rate (at 500 kb/s wclk = 1 mhz) ? the ds0 setup and hold time must be met by software.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 208 smsc lpc47m172 datasheet t9 t8 t7 t6 t4 t5 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 13.13 - epp 1.9 data or address write cycle name description min typ max units t1 nwait asserted to nwrite asserted (note 1) 60 185 ns t2 nwait asserted to nwrite change (note 1) 60 185 ns t3 nwait asserted to pdata invalid (note 1) 0 ns t4 pdata valid to command asserted 10 ns t5 nwrite to command asserted 5 35 ns t6 nwait asserted to command asserted (note 1) 60 210 ns t7 nwait deasserted to command deasserted (note 1) 60 190 ns t8 command asserted to nwait deasserted 0 10 us t9 command deasserted to nwait asserted 0 ns note 1: nwait must be filtered to compensat e for ringing on the parallel bus cable. nwait is considered to have settled after it does not transition for a minimum of 50 nsec.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 209 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t12 t11 t10 t9 t7 t8 t6 t5 t4 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 13.14 - epp 1.9 data or address read cycle name description min typ max units t1 nwait asserted to nwrite deasserted 0 185 ns t2 nwait asserted to nwrite modified (notes 1,2) 60 190 ns t3 nwait asserted to pdata hi-z (note 1) 60 180 ns t4 command asserted to pdata valid 0 ns t5 command deasserted to pdata hi-z 0 ns t6 nwait asserted to pdata driven (note 1) 60 190 ns t7 pdata hi-z to command asserted 0 30 ns t8 nwrite deasserted to command 1 ns t9 nwait asserted to command asserted 0 195 ns t10 nwait deasserted to command deasserted (note 1) 60 180 ns t11 pdata valid to nwait deasserted 0 ns t12 pdata hi-z to nwait asserted 0 s note 1: nwait is considered to have settled after it does not transition for a minimum of 50 ns. note 2: when not executing a write cycle, epp nwrite is inactive high.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 210 smsc lpc47m172 datasheet t5 t4 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 13.15 - epp 1.7 data or address write cycle name description min typ max units t1 command deasserted to nwrite change 0 40 ns t2 command deasserted to pdata invalid 50 ns t3 pdata valid to command asserted 10 35 ns t4 nwrite to command 5 35 ns t5 command deasserted to nwait deasserted 0 ns t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 13.16 - epp 1.7 data or address read cycle name description min typ max units t1 command asserted to pdata valid 0 ns t2 command deasserted to pdata hi-z 0 ns t3 command deasserted to nwait deasserted 0 ns
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 211 smsc/non-smsc register sets ( rev. 01-11-07) datasheet 13.1 ecp parallel port timing 13.1.1 parallel port fifo (mode 101) the standard parallel port is run at or near the peak 500kbytes/sec allowed in the forward direction using dma. the state machine does not ex amine nack and begins the next tr ansfer based on busy. refer to figure 13.17. 13.1.2 ecp parallel port timing the timing is designed to allow operation at approxim ately 2.0 mbytes/sec over a 15ft cable. if a shorter cable is used then the bandwidth will increase. 13.1.3 forward-idle when the host has no data to send it keeps hostclk (n strobe) high and the peripheral will leave periphclk (busy) low. 13.1.4 forward data transfer phase the interface transfers data and commands from the hos t to the peripheral using an interlocked periphack and hostclk. the peripheral may indicate its desire to send data to the host by asserting nperiphrequest. the forward data transfer phase may be entered from the forward-idle phase. while in the forward phase the peripheral may asynchronously assert the np eriphrequest (nfault) to request that the channel be reversed. when the peripheral is not busy it sets periphack (busy) low. the host then sets hostclk (nstrobe) low when it is prepared to send data. the dat a must be stable for the specified setup time prior to the falling edge of hostclk. the peripheral then sets periphack (busy) high to acknowledge the handshake. the host then sets hostclk (nstrobe) hi gh. the peripheral then accepts the data and sets periphack (busy) low, completing the transfer. this sequence is shown in figure 13.18. the timing is designed to provide 3 cable round-trip time s for data setup if data is driven simultaneously with hostclk (nstrobe). 13.1.5 reverse-idle phase the peripheral has no data to send and keeps periphclk high. the host is idle and keeps hostack low. 13.1.6 reverse data transfer phase the interface transfers data and commands from the per ipheral to the host using an interlocked hostack and periphclk. the reverse data transfer phase may be entered from t he reverse-idle phase. after the previous byte has been accepted the host sets hostack (nalf) low. the peripheral then sets periphclk (nack) low when it has data to send. the data must be stable for t he specified setup time prior to the falling edge of periphclk. when the host is ready to accept a byte it sets hostack (nalf) high to acknowledge the
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 212 smsc lpc47m172 datasheet handshake. the peripheral then sets periphclk (nack) high. after the host has accepted the data it sets hostack (nalf) low, completing the transfer. this sequence is shown in figure 13.19. 13.1.7 output drivers to facilitate higher performance data transfer, the use of balanced cmos active drivers for critical signals (data, hostack, hostclk, periphack, periphclk) are used in ecp mode. because the use of active drivers can present compatibility problems in compatible mode (t he control signals, by tradition, are specified as open-drain), the drivers are dynamically changed from o pen-drain to push-pull. the timing for the dynamic driver change is specified in then ieee 1284 exte nded capabilities port protocol and isa interface standard, rev. 1.14, july 14, 1993, available from microsoft. the dynamic driver change must be implemented properly to prev ent glitching the outputs. figure 13.17 - parallel port fifo timing name description min typ max units t1 pdata valid to nstrobe active 600 ns t2 nstrobe active pulse width 600 ns t3 pdata hold from nstrobe inactive (note 1) 450 ns t4 nstrobe active to busy active 500 ns t5 busy inactive to nstrobe active 680 ns t6 busy inactive to pdata invalid (note 1) 80 ns note 1: the data is held until busy goes inactive or for time t3, whichever is longer. this only applies if another data transfer is pending. if no other data transf er is pending, the data is held indefinitely. t3 t6 t1 t2 t5 t4 pd<7:0> nstrobe busy
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 213 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t3 t4 t1 t2 t7 t8 t6 t5 t6 nalf pd<7:0> busy nstrobe figure 13.18 - ecp parallel port forward timing name description min typ max units t1 nalf valid to nstrobe asserted 0 60 ns t2 pdata valid to nstrobe asserted 0 60 ns t3 busy deasserted to nalf changed (notes 1,2) 80 180 ns t4 busy deasserted to pdata changed (notes 1,2) 80 180 ns t5 nstrobe asserted to busy asserted 0 ns t6 nstrobe deasserted to busy deasserted 0 ns t7 busy deasserted to nstrobe asserted (notes 1,2) 80 200 ns t8 busy asserted to nstrobe deasserted (note 2) 80 180 ns note 1: maximum value only applies if there is data in the fifo waiting to be written out. note 2: busy is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 214 smsc lpc47m172 datasheet t2 t1 t5 t6 t4 t3 t4 pd<7:0> nack nalf figure 13.19 - ecp parallel port reverse timing name description min typ max units t1 pdata valid to nack asserted 0 ns t2 nalf deasserted to pdata changed 0 ns t3 nack asserted to nalf deasserted (notes 1,2) 80 200 ns t4 nack deasserted to nalf asserted (note 2) 80 200 ns t5 nalf asserted to nack asserted 0 ns t6 nalf deasserted to nack deasserted 0 ns note 1: maximum value only applies if there is room in the fifo and terminal count has not been received. ecp can stall by keeping nalf low. note 2: nack is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 215 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t2 t1 pci_clk ser_irq figure 13.20 - setup and hold time name description min typ max units t1 ser_irq setup time to pci_clk rising 7 nsec t2 ser_irq hold time to pci_clk rising 0 nsec data (5-8 bits) t1 data txd start parity stop (1-2 bits) figure 13.21 - serial port data name description min typ max units t1 serial port da ta bit time t br 1 nsec note 1: t br is 1/baud rate. the baud rate is programmed through the divisor latch registers. baud rates have percentage errors indicated in the ?baud rate ? table in the ?serial port? section.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 216 smsc lpc47m172 datasheet kclk/ mclk kdat/ mdat start bit bit 0 bit 7 clk 1 clk 2 clk 9 clk 10 t1 t6 t4 t3 clk 11 t5 parity bit stop bit t2 figure 13.22 - keyboard/mouse receive/send data timing name description min typ max units t1 time from data transition to falling edge of clock (receive) 5 25 sec t2 time from rising edge of clock to data transition (receive) 5 t4-5 sec t3 duration of clock inactive (receive/send) 30 50 sec t4 duration of clock active (receive/send) 30 50 sec t5 time to keyboard inhibit a fter clock 11 to ensure the keyboard does not start another transmission (receive) >0 50 sec t6 time from inactive to acti ve clock transition, used to time when the auxiliary device samples data (send) 5 25 sec
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 217 smsc/non-smsc register sets ( rev. 01-11-07) datasheet t3 t1 t2 fan_tachx figure 13.23 - fan tachometer input timing name description min typ max units t1 pulse time (1/2 revolution time=30/rpm) 11.11 sec t2 pulse high time 5.55 sec t3 pulse low time 5.55 sec led t1 t2 figure 13.24 - power led output timing name description min typ max units t1 period 1.49 sec t2 blink on time 0.59 sec
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 218 smsc lpc47m172 datasheet vcc/vtr vcc5v/v_5p0_stby ref5v/ref5v_stby 3.3v 3.3v 5v 5v 2.95v 3.3v (min) figure 13.25 - ref5v/ref5v_stby output when vcc/vtr ramps up befo re vcc5v/ v_5p0_stby note: the value 2.95v minimum in figure 13. 25 is (3.3 supply voltage ? 350 mv). vcc/vtr vcc5v/v_5p0_stby ref5v/ref5v_stby 3.3v 5v 5v figure 13.26 - ref5v/ref5v_stby output when vcc5v/ v_5p0_stby ramp s up before vcc/vtr
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 219 smsc/non-smsc register sets ( rev. 01-11-07) datasheet v c c / v t r vcc5v/v_5p0_stby ref5v/ref5v_stby 3.3v 5v 5v figure 13.27 - ref5v/ref5v_stby output when v cc/vtr ramps down before vcc5v/ v_5p0_stby vcc/vtr vcc5v/v_5p0_stby ref5v/ref5v_stby 3.3v 5v 5v 3.3v 2.95v 3.3v (min) figure 13.28 - ref5v/ref5v_stby output when v cc5v/ v_5p0_stby ramps down before vcc/vtr note: the value 2.95v minimum in figure 13. 28 is (3.3 supply voltage ? 350 mv).
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 220 smsc lpc47m172 datasheet a b tpropr tpropf tr tf figure 13.29 - rise, fall and propagation timings table 13.1 - nide_rstdrv timing name description (refer to figure 13.29) min typ max units tf nide_rstdrv (b) high to low fall time. measured form 90% to 10% 15 ns tpropf nide_rstdrv (b) high to low propagation time. measured from npci_reset (a) to nide_rstdrv (b). 20 ns co output capacitance 25 pf cl load capacitance 40 pf table 13.2 - npcirst_out and npcirst_out2 timing name description (refer to figure 13.29) min typ max units tr npcirst_out/npcirst_out2 (b) low to high rise time. measured form 10% to 90% 53 ns tpropr npcirst_out/npcirst_out2 (b) low to high propagation time. measured from npci_reset (a) to npcirst_out/npcirst_out2 (b). 30 ns co output capacitance 25 pf cl load capacitance 40 pf table 13.3 - ps_on timing name description (refer to figure 13.29) min typ max units tz nps_on (b) low to hi-z rise time. 50 ns tf nps_on (b) high to low fall time. measured form 90% to 10% 50 ns tpropz nps_on (b) low to hi-z propagation time. measured from nslp_s3 (a) to nps_on (b). 1 us tpropf nps_on (b) high to low propagation time. measured from nslp_s3 (a) to nps_on (b). 1 us co output capacitance 25 pf cl load capacitance 50 pf
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 221 smsc/non-smsc register sets ( rev. 01-11-07) datasheet table 13.4 - sck_bjt_gate timing name description (refer to figure 13.29) min typ max units tf sck_bjt_gate (b) low to high fall time. measured form 90% to 10% 50 ns tpropf sck_bjt_gate (b) high to low propagation time. measured from pwrgd_3v (a) to sck_bjt_gate (b). 1 us co output capacitance 25 pf cl load capacitance 50 pf table 13.5 - pwrgd_3v timing name description (refer to figure 13.29) min typ max units tr pwrgd_3v (b) low to high rise time. 50 ns tf pwrgd_3v (b) low to high fall time. measured form 90% to 10% 50 ns tpropr pwrgd_3v (b) low to high propagation time. measured from nfprst (a) to pwrgd_3v (b). 1 us tpropf pwrgd_3v (b) high to low propagation time. measured from nfprst (a) to pwrgd_3v (b). 1 us co output capacitance 25 pf cl load capacitance 50 pf table 13.6 - cnr codec down enable timing name description (refer to figure 13.29) min typ max units tr ncdc_dwn_rst (b) rise time. measured from 10% to 90%. 6 us tf ncdc_dwn_rst (b) fall time. measured from 90% to 10%. 6 us tpropr ncdc_dwn_rst (b) low to high propagation delay. measured from naud_lnk_rst (a) or ncdc_dwn_enab (a) to ncdc_dwn_rst (b). 15.3 ns tpropf ncdc_dwn_rst (b) high to low propagation delay. measured from naud_lnk_rst (a) or ncdc_dwn_enab (a) to ncdc_dwn_rst (b). 15.3 ns
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 222 smsc lpc47m172 datasheet v_5p0_stby nrsmrst t1 max min vtrip t2 t3 t4 vtr (3.3v) figure 13.30 - reseme reset sequence table 13.7 - resume reset timing name description min typ max units notes t1 treset delay. v_5p0_stby active to nrsmrst inactive 10 32 100 msec 1 t2 treset_fall. v_5p0_stby inactive to nrsmrst active (glitch width allowance) 100 nsec treset_rise 100 nsec t3 v_5p0_stby active to vtr active 0 msec 2 t4 v_5p0_stby inactive to vtr inactive 0 msec 2 v trip v_5p0_stby low trip voltage 4.2 4.5 v 3 note 1: the nrsmrst will be inactive high max 100 msec after v_5p0_stby is active assuming the vtr (3.3v) is active. if the vtr (3.3v) is not active within 100 msec, the delay from v_5p0_stby will be greater than 100 msec and the nrsmrst will go inactive when vtr (3.3v) goes active. note 2: the v_5p0_stby supply must power up before or simultaneous with vtr, and must power down simultaneous with or after vtr (from ich2 data sheet) note 3: the trip point can vary between these limits on a pe r part basis, but on a given part it should remain relatively stable.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 223 smsc/non-smsc register sets ( rev. 01-11-07) datasheet chapter 14 package outline figure 14.1 - 128 pin mqfp package ou tline, 14x20x2.7 body , 3.2mm footprint table 14.1 - 128 pin mqfp package parameters min nominal max remarks a ~ ~ 3.4 overall package height a1 0.05 ~ 0.5 standoff a2 2.55 ~ 3.05 body thickness d 23.00 23.20 23.40 x span d1 19.90 20.00 20.10 x body size e 17.00 17.20 17.40 y span e1 13.90 14.00 14.10 y body size h 0.09 ~ 0.20 lead frame thickness l 0.73 0.88 1.03 lead foot length l1 ~ 1.60 ~ lead length e 0.50 basic lead pitch 0 o ~ 7 o lead foot angle w 0.10 ~ 0.30 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.30 lead foot radius ccc ~ ~ 0.08 coplanarity notes: 1. controlling unit: millimeter. 2. tolerance on the position of the leads is 0.04 mm maximum. 3. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. 4. dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane. 5. details of pin 1 identifier are optional but must be located within the zone indicated.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 224 smsc lpc47m172 datasheet chapter 15 board test mode board level testing is implemented with an xor ch ain. the xor chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to vcc or gnd). the test_en pin is used as a strap pin to enter test mode. this pin has an internal 30 a pull-down resistor to vss. an external 10 kohm pull-up to v_3p3_stby is used to put the device in test mode. both vcc and vtr supplies are required for the device to operate properly in test mode. the part enters board test (xor-chain) mode when the test_en pin is brought high. the part remains in test mode while test_en is high. bri nging test_en low will exit test mode. when the xor chain is entered, all output and bi-directional buffers wi thin that chain are tri-stated, except for the xor chain output. every signal in the xor ch ain (except for the xor chain?s output) functions as an input. figure 15.1 is a schematic example of xor chain circuitry. vcc3 input pin 1 input pin 2 input pin 3 input pin 4 input pin 5 xor chain output figure 15.1 - example xor chain circuitry the xor chain output is on pin 30, ndtr1/xor. the input pin ordering is as follows: the first input pin in the xor chain is pin 1 of the chip (mclk), and the order continues around the chip in increasing pin number order to end at pin 128, skipping those pins that are excluded from the chain. the following pins are excluded from the xor chain. ? nrsmrst pin (1) ? ref5v pin (1) ? ref5v_stby pin (1) ? vcc pins (5) ? vtr pins (4) ? v_5p0_stby pin (1) ? vss pins (7) ? f_cap pin (1) ? ndtr1/xor pin (1) ? test_en pin (1) the total number of pins excluded from the xor chain is 23; therefore there are an odd number of pins in the xor chain.
advanced i/o controller with motherboard glue logic datasheet smsc lpc47m172 page 225 smsc/non-smsc register sets ( rev. 01-11-07) datasheet xor chain testability algorithm example an example algorithm for using the xor chain for board test is shown below. table 15.1 - xor test pattern example test vector input pin 1 input pin 2 input pin 3 input pin 4 input pin 5 xor output 1 0 0 0 0 0 1 2 1 0 0 0 0 0 3 1 1 0 0 0 1 4 1 1 1 0 0 0 5 1 1 1 1 0 1 6 1 1 1 1 1 0 in this example, vector 1 applies all "0s" to t he chain inputs. the outputs being non-inverting, will consistently produce a "1" at the xor output on a good board. one short to vcc (or open floating to vcc) will result in a "0" at the chain output, signaling a defect. likewise, applying vector 6 (all "1s") to the chain input s (given that there is an odd number of input signals in the chain) will consistently pr oduce a "0" at the xor chain output on a good board. one short to vss (or open floating to vss) will result in a "1" at the chain output, signaling a defect. it is important to note that the number of inputs pulled to "1 " will affect the chain output valu e. if the number of chain inputs pulled to "1" is even, then a "1" will be seen at the out put. if the number of chain inputs pulled to "1" is odd, a "0" will be seen at the output. continuing with the example in table 15.1, as the input pins are driven to "1" across the chain in sequence, the xor output will toggle between "0" and "1." any break in the toggling sequence (e.g., "1011") will identify the location of the short or open.
advanced i/o controller with motherboard glue logic datasheet smsc/non-smsc register sets ( rev. 01-11-07) page 226 smsc lpc47m172 datasheet chapter 16 reference documents 1. ieee 1284 extended capabilities port protocol and isa standard, rev. 1.14, july 14, 1993. 2. hardware description of the 8042, intel 8 bit embedded controller handbook. 3. pci bus power management interface specif ication, rev. 1.0, draft, march 18, 1997. 4. low pin count (lpc) interface specification, revision 1.0, september 29, 1997, intel document. 5. metalious acpi/manageability spec ification, v1.0, aril 30, 1999 6. advanced configuration and powe r interface specification, v 1.0 7. smsc application note, an 8-8: using the enhanced keyboard and mouse wakeup feature in smsc super i/o parts. 8. smsc application note, an 9-3: application cons iderations when using the powerdown feature of smsc floppy disk controllers.

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